參數(shù)資料
型號(hào)： ORLI10G-3BM416
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA416
封裝： PLASTIC, BGA-416
文件頁(yè)數(shù)： 3/76頁(yè)
文件大小： 1222K
代理商： ORLI10G-3BM416
Lattice Semiconductor
11
Data Sheet
January 15, 2002
and ORLI12G Gbits/s Line Interface FPSC
ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s
System-Level Features (continued)
Conguration
The FPGAs functionality is determined by internal con-
guration RAM. The FPGAs internal initialization/con-
guration circuitry loads the conguration data at
powerup or under system control. The conguration
data can reside externally in an EEPROM or any other
storage media. Serial EEPROMs provide a simple, low,
pin-count method for conguring FPGAs.
The RAM is loaded by using one of several congura-
tion modes. Supporting the traditional master/slave
serial, master/slave parallel, and asynchronous periph-
eral modes, the Series 4 also utilizes its microproces-
sor interface and embedded system bus to perform
both programming and readback. Daisy chaining of
multiple devices and partial reconguration are also
permitted.
Other conguration options include the initialization of
the embedded-block RAM memories and FPSC mem-
ory as well as system bus options and bit stream error
checking. Programming and readback through the
JTAG (IEEE 1149.2) port is also available meeting in-
system programming (ISP) standards (IEEE 1532
Draft).
Additional Information
Contact your local Lattice representative for additional
information regarding the ORCA Series 4 FPGA
devices, or visit our website at:
http://www.latticesemi.com
ORLI10G Overview
Device Layout
The ORLI10G FPSC provides a high-speed transmit
and receive line interface combined with FPGA logic.
The device is based on the 1.5 V OR4E4 FPGA. The
ORLI10G consists of an embedded backplane trans-
ceiver core and a full OR4E4 36x36 FPGA array.
The ORLI10G is a line interface device that contains an
FPGA base array, a 10 Gbits/s line interface block, and
programmable PLLs to do the overhead clock rate con-
versions on a single monolithic chip. The embedded
portion includes:
■
Line Interface: This consists of a 16-bit LVDS receive
data bus and a 16-bit LVDS transmit bus operating
up to 850 Mbits/s per input/output pair. Each 4-bit
LVDS I/O has a high-speed LVDS clock (operating up
to 850 MHz) associated with it. The bit order (i.e.
whether bit 0 is the most signicant or least signi-
cant bit) of the 16-bit transmitted and received bus-
ses can be dened separately in the user's
programmable logic netlist that interfaces to the
embedded core so that any required interface stan-
dard can be met.
■
MUX/deMUX: This performs the MUXing and
deMUXing between the high-speed line interface
data operating at the line rate and system data oper-
ating at 1/4 or 1/8 the line rate.
■
On-board PLLs: This is used to align system-side
data with the line-side data, which is at a slightly
higher data bandwidth than the system data because
of the addition of overhead due to encoding.
Figure 1 shows the ORLI10G block diagram.
10G Mode
The ORLI10G can operate in one of two data modes:
10G mode or Quad 2.5G mode.
In 10G (or single-channel) mode, all 16 LVDS transmit
data outputs are assumed to be one data bus with one
LVDS clock provided off chip for the data. Likewise, all
16 LVDS receive data inputs are assumed to be one
data bus with one LVDS input clock provided for the
data.
Transmit Path
In 10G mode, the transmit data from the FPGA logic is
passed to the embedded core as a single 128- or 64-bit
bus. An off-chip transmit reference clock is divided
down in the core by 8 (for 128-bit to 16-bit MUX) or by 4
(for 64-bit to 16-bit MUX). All four transmit clock outputs
are therefore synchronized.
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