參數(shù)資料
型號： ORSO42G5-EV
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 15/153頁
文件大?。?/td> 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
標(biāo)準(zhǔn)包裝： 1
系列： ORCA® 4 系列
類型： FPGA
適用于相關(guān)產(chǎn)品： ORSO42G5
所含物品： 板，線纜，電源
其它名稱： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
111
Input Eye-Mask Characterization
Figure 51 provides an eye-mask characterization of the SERDES receiver input. The eye-mask is specied below
for two different eye-mask heights. It provides guidance on a number of input parameters, including signal ampli-
tude and rise time limits, noise and jitter limits, and P and N input skew tolerance. Almost all detrimental character-
istics of transmit signal and the interconnection link design result in eye-closure. This, combined with the eye-
opening limitations of the line receiver, can provide a good indication of a link’s ability to transfer data error-free.
The Clock and Data Recovery (CDR) portion of the ORSO42G5 and ORSO82G5 SERDES receiver has the ability
to lter incoming signal jitter that is below the clock recovery PLL bandwidth (about 3 MHz). The eye-mask speci-
cations of Table 45 are for jitter frequencies above the PLL bandwidth of the CDR, which is a worst case condition.
When jitter occurs at frequencies below the PLL bandwidth, the receiver jitter tolerance is signicantly better. For
this case error-free data detection can occur even with a completely closed eye-mask.
Figure 51. Receive Data Eye-Diagram Template (Differential)
Table 45. Receiver Eye-Mask Specications1
Parameter
Conditions
Value
Unit
Input Data
Eye Opening Width (H)@ 2.7Gbps
V=175 mV diff
1
0.55
UIP-P
Eye Opening Width (T)@ 2.7Gbps
V=175 mV diff
1
0.15
UIP-P
Eye Opening Width (H)@ 2.7Gbps
V=600 mV diff
1
0.35
UIP-P
Eye Opening Width (T)@ 2.7Gbps
V=600 mV diff
1
0.10
UIP-P
Eye Opening Width (H)@ 2.5Gbps
V=175 mV diff
1
0.42
UIP-P
Eye Opening Width (T)@ 2.5Gbps
V=175 mV diff
1
0.15
UIP-P
Eye Opening Width (H)@ 2.5Gbps
V=600 mV diff
1
0.33
UIP-P
Eye Opening Width (T)@ 2.5Gbps
V=600 mV diff
1
0.10
UIP-P
1. With PRBS 2^7-1 data pattern, 10 MHz sinusoidal jitter, all channels operating, FPGA logic active, REFCLK jitter
of 30 ps., TA = 0
oC to 85oC, 1.425V to 1.575V supply.
H
V
1.2 V
UI
T
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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