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| 型號(hào)： | ORSO82G5-1F680I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 72/153頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
25
ation will be based on the system frame pulse (DINxx_FP) received from the FPGA logic, hence it is recommended
that, for multi-channel alignment at the receiver, the frame pulses for the channels in an alignment group be syn-
chronized. The data are then scrambled before being sent to the SERDES.
In the receive direction, the two SONET blocks process the receiving channels which can be treated as STS-192
streams or as independent STS-48 streams.The clocks for the received data are recovered from the received serial
data streams and a serial to parallel conversion is performed on the data. The frame format of the incoming data
are reconstructed (optional). The data then is descrambled using the standard SONET polynomial and a B1 parity
error check is performed on the data from the previously transmitted frame.
In the SONET mode, the incoming serial data streams can be aligned by groups of two, four or, in the ORSO82G5,
eight. When doing multichannel alignment of two or more data streams, the receiver can handle the data streams
with frame offsets of up to 18 78MHz clock cycles due to timing skews between cards and along backplane traces
or other transmission medium. For multichannel alignment capability to operate properly, it should be noted that
while the skew between channels can be very large, they must operate at the exact same frequency (0 ppm fre-
quency deviation), thus requiring that the transmitters sourcing the data being received be driven by the same clock
source. It is highly recommended that the frame pulses, DINxx_FP, for all links in an alignment group be synchro-
nized. (See Table 11 and Table 12 for details of the core/FPGA transmit direction signal assignments.)
The received data streams are processed and passed to the FPGA logic as 32-bit words. In SONET mode,
DOUTxx[31:0] carries the 32 bit data from the alignment FIFO of the respective channel and an accompanying
frame pulse, DOUTxx_FP. Other core/FPGA carries miscellaneous information such as OOF, BIPERR, and SPE
Basic SONET Frame Format
An STS-N frame can be broadly divided into the Transport OverHead (TOH) and the Synchronous Payload Enve-
lope (SPE) areas. The TOH comprises of bytes that are used for framing, error detection and various other func-
pointer bytes located in the TOH. The basic STS-1 frame is shown in Figure 12. Higher rate STS_N signals are cre-
ated by byte interleaving N STS-1 signals. Some TOH bytes have slightly different functions in STS-N frames than
in the basic STS-1 frame. The ORSO42G5 and ORSO82G5 offer two options for processing the TOH bytes, as dis-
cussed in a later section.
Figure 12. STS-1 Frame Format
Transport
OverHead
(TOH)
Synchronous Payload Envelope
(SPE)
3 columns
90 Columns
9 Rows
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO82G5-1FN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 1.5V 2.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1FN680C1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1FN680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 ORCA FPSC 2.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-1FN680I1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO82G5-2BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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