參數(shù)資料
型號： ORT82G5-1BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 39/110頁
文件大小： 1459K
代理商： ORT82G5-1BM680
34
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed
Description (continued)
To resynchronize a multichannel alignment group set
the following bit to zero, and then set it to 1.
■
FMPU_RESYNC8 for eight channel A[A:D] and
B[A:D]
■
FMPU_RESYNC4A for quad channel A[A:D]
■
FMPU_RESYNC2A1 for twin channel A[A:B]
■
FMPU_RESYNC2A2 for twin channel A[C:D]
■
FMPU_RESYNC4B for quad channel B[A:D]
■
FMPU_RESYNC2B1 for twin channel B[A:B]
■
FMPU_RESYNC2B2 for twin channel B[C:D]
To resynchronize an independent channel (resetting
the write and the read pointer of the FIFO) set the fol-
lowing bit to zero, and then set it to 1.
■
FMPU_RESYNC1_xx where xx is one of A[A:D] and
B[A:D]
A two-to-one multiplexor is used to select between
aligned or nonaligned data to be sent to the FPGA on
MRWDxy[39:0]. With x representing the bank (place-
holder for A or B) and y representing the channel
(placeholder for A, B, C or D), the 40-bit MRWDxy[39:0]
is allocated as shown in Table 10.
Alignment Sequence
1.
Follow steps 1 and 2 in the start up sequence
described previously.
2.
Initiate a SERDES software reset by setting the
SWRST bit to 1 and then to 0. Note that, any
changes to the SERDES conguration bits should
be followed by a software reset.
3.
Wait for 3 ms. REFCLK should be toggling by this
time. During this time, congure the following regis-
ters.
Set the following bits in registers 30820, 30920
■
XAUI_MODEx-set to 1 for XAUI mode or keep the
default value of 0.
Enable channel alignment by setting
FMPU_SYNMODE bits in registers 30811, 30911.
■
FMPU_SYNMODE_xx. Set to appropriate val-
ues for 2, 4, or 8 alignment based on Table 11.
Set RCLKSELx and TCKSELx bits in registers
30A00.
■
RCKSELx-choose clock source for 78 MHz RCK78x
■
TCKSELx-Choose clock source for 78 MHz
TCK78x (Table 8).
4.
Send data on serial links. Monitor the following sta-
tus/alarm bits:
Monitor the following alarm bits in registers 30000,
30010, 30020, 30030, 30100, 30110, 30120,
30130.
■
LKI-PLL lock indicator. A 1 indicates that PLL has
achieved lock.
Monitor the following status bits in registers 30804,
30904
■
XAUISTAT_xx - In XAUI mode, they should be 10.
Monitor the following status bits in registers 30805,
30905
■
DEMUXWAS_xx-They should be 1 indicating word
alignment is achieved.
■
CH248_SYNCxx-They should be 1 indicating chan-
nel alignment. This is cleared by resync.
5.
Write a 1 to the appropriate resync registers
30820, 30920. Note that this assumes that the pre-
vious value of the resync bits are 0. The resync
operation requires a rising edge. Two writes are
required to the resync bits: write a 0 and then write
a 1.
Check out-of-sync and FIFO overow status in reg-
isters 30814 (Bank A).
■
SYNC4_A_OOS, SYNC4_A_OVFL-by 4 align-
ment.
■
SYNC2_A2_OOS, SYNC_A2_OVFL or
SYNC2_A!_OOS, SYNC2_A!_OVFL-by 2 align-
ment.
Check out-of-sync status in registers 30914 (Bank
B).
■
SYNC4_B_OOS, SYNC4_B_OVFL-by 4 align-
ment.
■
SYNC_B2_OOS, SYNC2_B2_OVFL or
SYNC2_B1_OOS, SYNC_B1_OVFL-by 2 align-
ment.
Check out-of-sync status in register 30A03
■
SYNC8_OOS, SYNC8_OVFL-by 8 alignment.
■
If out-of-sync bit is 1, then rewrite a 1 to the appropri-
ate resync registers and monitor the OOS bit again.
If out-of-sync (OOS) bit is 0 but OVFL bit is 1, then
check if the RX_FIFO_MIN value has been pro-
grammed to a value > 0. (Default value is 0.) Change
the value to 0 and check the OVFL bit again. If OOS
and OVFL are 1, then rewrite a 1 to the appropriate
resync registers. The resync operation requires a ris-
ing edge. Two writes are required to the resync bits:
write a 0 and then write a 1.
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參數(shù)描述
ORT82G5-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 3.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-1FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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