參數(shù)資料
型號： ORT82G5-3BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 57/110頁
文件大?。?/td> 1459K
代理商： ORT82G5-3BM680
50
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
For XAUISTAT_Ay[0:1] (address 0x30804), the denitions of these bits are:
00—No synchronization.
10—Synchronization done.
01,11—Not used.
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
Status Registers A
30804
A16
XAUISTAT_AA[0:1]
Status of XAUI link state
machine for bank A, channel A
XAUISTAT_AB[0:1]*
Status of XAUI link state
machine for bank A, channel B
XAUISTAT_AC[0:1]*
Status of XAUI link state
machine for bank A, channel C
XAUISTAT_AD[0:1]*
Status of XAUI link state
machine for bank A, channel D
00
30805
A17
DEMUXWAS_
AA
Status of
deMUX word
alignment for
bank A, chan-
nel A
DEMUXWAS_
AB
Status of
deMUX word
alignment for
bank A, chan-
nel B
DEMUXWAS_
AC
Status of
deMUX word
alignment for
bank A, chan-
nel C
DEMUXWAS
_AD
Status of
deMUX word
alignment for
bank A, chan-
nel D
CH248_SYNC
_AA
Alignment
completed for
AA
CH248_SYNC
_AB
Alignment
completed for
AB
CH248_SYNC
_AC
Alignment
completed for
AC
CH248_SYNC
_AD
Alignment
completed for
AD
00
30806
A18
Reserved for future use
30807
A19
Reserved for future use
30814
A20
SYNC2_A1
OVFL
Alignment
FIFO over-
ow AA and
AB
SYNC2_A2
OVFL
Alignment
FIFO over-
ow AC and
AD
SYNC4_A
OVFL
Alignment
FIFO over-
ow for A[A:D]
SYNC2_A1
OOS
Alignment out
of sync for AA
and AB
SYNC2_A2
OOS
Alignment out
of sync for AC
and AD
SYNC4_A_O
OS
Alignment out
of sync for
A[A:D]
Reserved for future use
30815
A21
Reserved for future use
30816
A22
Reserved for future use
30817
A23
Reserved for future use
30824
A24
Reserved for future use
30825
A25
Reserved for future use
30826
A26
Reserved for future use
30827
A27
Reserved for future use
30834
A28
Reserved for future use
30835
A29
Reserved for future use
30836
A30
Reserved for future use
30837
A31
Reserved for future use
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT82G5-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3BM680C2 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 3.7 Gbps XAUI and FC FPSCs
ORT82G5-3F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-3FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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