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OV7620 Product Specifications - Rev. 1.2 (5/13/00)
OMNIVISION TECHNOLOGIES INC.
34
Preliminary
Company Confidential
Register 17 - rw: Horizontal Window start
HS<7:0> - selects the starting point of HREF window, each LSB represents four pixels for Inter-
laced/Progressive full resolution mode, two pixels for QVGA resolution mode, this value is set
based on an internal column counter, the default value corresponds to 640 horizontal window.
Maximum window size is 664. see window description below. HS<7:0> programmable range
is [2C]- [D2], and should less than HE<7:0>. HS<7:0> should be programmable to value larger
than or equal to [2C]. Value larger than [D2] is invalid. See Figure 1.14.
Register 18 - rw: Horizontal Window end
HE<7:0> - selects the ending point of HREF window, each LSB represents four pixels for full resolution
and two pixels for QVGA resolution, this value is set based on an internal column counter, the
default value corresponds to the last available pixel. The HE<7:0> programmable range is
[2D] - [D2]. HE<7:0> should be larger than HS<7:0> and less than or equal to [D2]. Value
larger than [D2] is invalid. See Figure 1.14.
Register 19- rw: Vertical Window start
VS<7:0> - selects the starting row of vertical window, in full resolution mode, each LSB represents 1scan
line in one field for Interlaced Mode, 2 scan line in one frame for Progressive Scan Mode. In
QVGA resolution (set by register 14 bit 5), each LSB represents 1 scan line in one field for
Interlaced Mode, 1scan line in one frame for Progressive Scan Mode. See Figure 1.14. Min. is
[05], max. is [F6] and should less than VE<7:0>.
VE<7:0>- selects the ending row of vertical window, in full resolution mode, each LSB represents 1scan
line in one field for Interlaced Mode, 2 scan line in one frame for Progressive Scan Mode. In
QVGA resolution, each LSB represents 1 scan line in one field for Interlaced Mode, 1scan line
in one frame for Progressive Scan Mode. See Figure 1.14. Min. is [05], max. is [F6] and should
larger than VS<7:0>.
Bits
HS7
HS6
HS5
HS4
HS3
HS2
HS1
HS0
Default
0
0
1
0
1
1
1
1
Bits
HE7
HE6
HE5
HE4
HE3
HE2
HE1
HE0
Default
1
1
0
0
1
1
1
1
Bits
VS7
VS6
VS5
VS4
VS3
VS2
VS1
VS0
Default
0
0
0
0
0
1
1
0
Register 1A- rw: Vertical Window end
Bits
VE7
VE6
VE5
VE4
VE3
VE2
VE1
VE0
Default
1
1
1
1
0
1
0
1