參數(shù)資料
型號(hào)： OV8110
廠商： Electronic Theatre Controls, Inc.
英文描述： Advanced Information Preliminary
中文描述： 先進(jìn)的信息初步
文件頁(yè)數(shù)： 16/28頁(yè)
文件大小： 180K
代理商： OV8110
Advanc ed Information
Preliminary
OV 8610/OV 8110
OV 8610 S INGLE-CHIP CMOS V GA COLOR DIGIT AL CAMERA
OV 8110 S INGLE-CHIP CMOS V GA B&W DIGIT AL CAMERA
OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A.
Tel: (408) 733-3030 Fax: (408) 733-3061
e-mail:
info@ovt.com
Website: http://www.ovt.com
Version 1.3, August 27, 2001
Page 16
Frame Exposure Mode
OV8610/OV8110 supports frame exposure mode when FREX
is set high. PWDN is asserted by an external master device to
set exposure time at this mode. The pixel array is quickly pre-
charged when PWDN is set to “1”. OV8610/OV8110 captures
the image in the time period when PWDN remains high. The
video data stream is delivered to output port in a line-by-line
manner after PWDN switches to “0”.
It should be noted that PWDN must remain high long enough to
ensure the entire image array has been pre-charged.
Reset
OV8610/8110 includes a RESET pin (pin 2) that forces a
complete hardware reset when it is pulled high (VCC).
OV8610/8110 clears all registers and resets to their default
values when a hardware reset occurs. Reset can also be
initiated through the SCCB interface.
Power Down Mode
Two methods are available to place OV8610 into power-down
mode: hardware power-down and SCCB software power-down.
To initiate hardware power-down, the PWDN pin (9) must be
tied to high (+3.3VDC). When this occurs, the OV8610 internal
device clock is halted and all internal counters are reset. The
current draw is less than 10
μ
A in this standby mode.
Executing a software power-down through the SCCB interface
suspends internal circuit activity, but does not halt the device
clock. The current requirements drop to less than 1mA in this
mode.
Configure OV8610/OV8110
The method to configure OV8610/OV8110 is to use its on-chip
SCCB register programming capability. The SCCB interface
provides access to all of the device’s programmable internal
registers.
FREX
DATA
OUTPUT
HSYNC
VSYNC
ARRAY
PRECHARGE
HREF
Invalid Data
T
SET
T
HD
1 Frame (612 Lines) Valid Data
Mechanical Shutter Off
T
IN
Array Exposure Period T
EX
Precharge begins at the rising edge of HSYNC
T
PR
Array Precharge Period T
PR
Head of Valid Data (8 Lines)
Next Frame
T
HS
Black Data
Note:
#
T
=824 x 4 x T
or T
=858xT
clk
depends on mode selecton. T
is internal pixel period. T
CLK
=50ns
if the system clock is 20MHz . T
will increase with the clock divider CLK[5:0].
#
T
EX
is array exposure time which is decided by external master device.
#
T
is uncertain time due to the using of HSYNC rising edge to synchronize FREX. T
< T
.
#
There are 8 lines data output before valid data after FREX=0. T
HD
=4 THS. Valid data is output when
HREF=1.
#
T
=T
+ T
+ T
EX
. T
SET
> T
PR
+ T
IN
. The exposure time setting resolution is T
HS
(one line) due to the
uncertainty of T
IN
.
Figure 8. Frame Exposure Timing
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