參數(shù)資料
型號： OX12PCI840
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Parallel Port and PCI interface
中文描述： 集成的并行端口和PCI接口
文件頁數(shù)： 2/32頁
文件大?。?/td> 541K
代理商： OX12PCI840
Data Sheet Revision 1.2
Page 2
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
C
ONTENTS
1
2
3
4
4.1
4.2
4.2.1
4.3
4.3.1
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.5
4.6
4.6.1
5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
7
PIN INFORMATION.....................................................................................................................4
PIN DESCRIPTIONS....................................................................................................................5
CONFIGURATION & OPERATION...............................................................................................8
PCI TARGET CONTROLLER.......................................................................................................9
OPERATION..........................................................................................................................................................................9
CONFIGURATION SPACE...................................................................................................................................................9
PCI CONFIGURATION SPACE REGISTER MAP .........................................................................................................10
ACCESSING LOGICAL FUNCTIONS................................................................................................................................11
PCI ACCESS TO PARALLEL PORT..............................................................................................................................11
ACCESSING LOCAL CONFIGURATION REGISTERS ....................................................................................................12
LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00).........................................................12
MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04)............................................................. 13
LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): ...................................................................13
LOCAL BUS TIMING PARAMETER/BAR SIZING REGISTER 2 ‘LT2’ (OFFSET 0X0C):.............................................14
GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X10).................................................15
PCI INTERRUPTS ...............................................................................................................................................................16
POWER MANAGEMENT....................................................................................................................................................17
POWER MANAGEMENT USING MIO............................................................................................................................ 17
BI-DIRECTIONAL PARALLEL PORT..........................................................................................18
OPERATION AND MODE SELECTION............................................................................................................................. 18
SPP MODE......................................................................................................................................................................18
PS2 MODE......................................................................................................................................................................18
EPP MODE......................................................................................................................................................................18
ECP MODE......................................................................................................................................................................18
PARALLEL PORT INTERRUPT.........................................................................................................................................18
REGISTER DESCRIPTION.................................................................................................................................................19
PARALLEL PORT DATA REGISTER ‘PDR’...................................................................................................................19
ECP FIFO ADDRESS / RLE ...........................................................................................................................................19
DEVICE STATUS REGISTER ‘DSR’..............................................................................................................................19
DEVICE CONTROL REGISTER ‘DCR’ ..........................................................................................................................20
EPP ADDRESS REGISTER ‘EPPA’...............................................................................................................................20
EPP DATA REGISTERS ‘EPPD1-4’...............................................................................................................................20
ECP DATA FIFO............................................................................................................................................................. 20
TEST FIFO......................................................................................................................................................................20
CONFIGURATION A REGISTER ...................................................................................................................................20
CONFIGURATION B REGISTER ...................................................................................................................................21
EXTENDED CONTROL REGISTER ‘ECR’....................................................................................................................21
SERIAL EEPROM......................................................................................................................22
SPECIFICATION.................................................................................................................................................................22
EEPROM DATA ORGANISATION.....................................................................................................................................22
ZONE0: HEADER............................................................................................................................................................ 22
ZONE1: LOCAL CONFIGURATION REGISTERS .........................................................................................................23
ZONE2: IDENTIFICATION REGISTERS........................................................................................................................23
ZONE3: PCI CONFIGURATION REGISTERS ...............................................................................................................23
ZONE4: FUNCTION ACCESS........................................................................................................................................ 25
OPERATING CONDITIONS........................................................................................................26
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相關代理商/技術參數(shù)
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