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參數(shù)資料
| 型號： | P11997EJ2V0AN00 |
| 英文描述： | uPC2757. uPC2758. and uPC8112. 3-V Power Supply. 1.9-GHz Frequency Down-converter ICs for Mobile Communication |
| 中文描述： | uPC2757。 uPC2758。和uPC8112。 3 - V單電源供電。 1.9 - GHz的頻率下，移動(dòng)通信轉(zhuǎn)換器IC |
| 文件頁數(shù)： | 20/51頁 |
| 文件大?。?/td> | 265K |
| 代理商： | P11997EJ2V0AN00 |
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Application Note P11997EJ2V0AN00
20
Figure 4-5. External Circuit Configurations for Output Ports
μ
PC2757, 2758
μ
PC8112
5
3 V
C
C
50
6
V
CC
IF
out
Example shows next-stage
impedance of 50
5
3 V
L
C
C
6
V
CC
IF
out
Constant is determined according
to next-stage impedance
4.3 Description of Application Circuit Characteristics
(1)
μ
PC2757 and
μ
PC2758
Since only the input pins can determine the characteristics for these two product models, this section describes
in detail the application characteristics that depend on the input pins’ external connections.
Figures 4-6 and 4-7 show measurement results for three measurement conditions affecting the RF input pin:
when using the matching method (<1>), when using the 50-
termination method (<2>), and when using the
data sheet’s test circuit. The output intercept point is almost the same no matter which measurement condition
is used. However, the matching method’s conversion gain value is 5 to 6 dB higher than the corresponding
value in the data sheet characteristics and about 4 to 6 dB lower than when using the 50-
termination method.
Also, variation of IM
3
in the input conversion is worsened when using the matching method (<1>) which
multiplies only the IM
3
gradient (
IM
3
) in relation to input and is improved when using the 50-
termination
method (<2>).
This behavior occurs when the previous stage’s characteristic impedance is 50
(or a value close to 50
),
and the characteristics are thought to approximate the data sheet characteristics when there is high impedance.
In the RF input, we recommend using the matching method (<1>) when emphasizing conversion gain pin and
we recommend using the 50-
termination method (<2>) when emphasizing input conversion distortion. The
trade-offs are between improving VSWR and IIP
3
characteristics vs. lowering the CG and worsening the noise
figure.
When using either method in the LO input pin, LO input level range of the CG flat or minimum noise figure
shifts, so the method should be determined according to your LO input level.
(2)
μ
PC8112
In the
μ
PC8112, connecting an external matching circuit to the IF output pin can optimize the output return loss
at the desired IF frequency to about
20 dB to obtain an IP
3
value for output conversion. A high-pass type
circuit that includes parallel inductance and serial capacitance is used as the matching circuit configuration.
Another objective is to apply a collector bias having the same potential as the V
CC
to the internal transistors
through the parallel inductor.
In this case, varying high-frequency characteristics depend on the circuit Q of the matching circuit. Even if the
inductor’s Q value is high, such as 60, the load Q is reduced and the desired frequency’s output return loss
becomes about
20 dB at 3.0 V, which is a gradual S
22
in relation to the comparative frequency. Figures 4-8
and 4-9 show Smith charts and log MAGs of 100-MHz matching for the IF port. Even when the inductor’s Q
value is low (such as 20), if load Q becomes high, the desired frequency’s output return loss becomes about
27 dB at 3.0 V, which means that the S
22
is much sharper in the desired frequency and the CG is slightly
(about 2 or 3 dB) higher compared to the data sheet’s test circuit, which raises the IM
3
level proportionately.
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