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參數(shù)資料
| 型號： | P1819A-08SR |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Low Power Mobile VGA EMI Reduction IC |
| 中文描述： | 40 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 60K |
| 代理商： | P1819A-08SR |
Low Power Mobile VGA EMI Reduction IC
4 of 8
March 2003
P1818/19/20/21/22
Notice: The information in this document is subject to change without notice.
Frequency vs. Deviation (P1818A and P1818H)
Pin Description
Frequency
Deviation in P1818A
Deviation in P1818H
SRS = 1
SRS = 0
D_C = 1
D_C = 0
10 MHz
-4.4%
-3.3%
-4.4%
±2.2%
15 MHz
-1.8%
-1.26%
-1.8%
±0.9%
20 MHz
-0.8%
-0.6%
-0.8%
±0.4%
Pin
number
Name
Type
Description
1
XIN
I
Connect to externally generated clock signal or crystal.
2
VSS
P
Ground Connection. Connect to system ground.
3
SRS
I
Spread Range Select. Digital logic input used to select frequency devi-
ation (see Spread Deviation Selections). This pin has an internal pull-
up resistor.
3
1
1. Please refer to Figure 1 for pin assignment.
D_C
I
Digital logic input used to select Down (LOW) or Center (HIGH) Spread
Options (see Spread Deviation Selections). This pin has an internal
pull-up resistor.
4
ModOut
O
Spread Spectrum clock output (see Input Frequency and Modulation
Rate Selections and Spread Deviation Selections).
5
REF
O
Non-modulated reference output clock of the input frequency.
5/6
1
FRS
I
Frequency Range Select. Digital logic input used to select input fre-
quency range (see Input Frequency and Modulation Rate Selections).
This pin has an internal pull-up resistor.
6
1
PD#
I
Power-Down control pin. Pull LOW to enable Power-Down mode. This
pin has an internal pull-up resistor.
7
VDD
P
Connect to +3.3V
8
XOUT
I
Connect to crystal. No connect if externally generated clock signal is
used.
8
1
MRS
I
Modulation Rate Select. Digital logic input used to select Modulation
Rate (see Spread Deviation Selections). This pin has an internal pull-
up resistor.
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