參數(shù)資料
型號(hào): P2005X-08ST
廠商: Alliance Semiconductor Corporation
英文描述: Low Frequency EMI Reduction IC
中文描述: 低頻電磁干擾降低集成電路
文件頁(yè)數(shù): 2/10頁(yè)
文件大?。?/td> 459K
代理商: P2005X-08ST
October 2003
rev 1.0
Pin Configuration
Pin Description
P2005X
General purpose EMI Reduction IC
2 of 10
Notice: The information in this document is subject to change without notice.
XOUT
1
2
3
4
5
6
7
8
P2005X
XIN /CLK
DIV2
VSS
SR0
SSON#
ModOUT
VDD
Pin#
Pin
Name
XIN/CLK
Type
Description
1
I
Connect to crystal or clock.
2
XOUT
O
Crystal output.
Digital logic input used to select normal output mode or divide-by-two output mode.
When this pin is HIGH, the frequency of the output clock is the same as the input
clock frequency. When it is tied low, the output frequency is half the input clock
frequency. This pin has an internal pull-up resistor.
Ground to entire chip. Connect to system ground.
Digital logic input used to select Spreading Range
Refer Modulation Output and
Spreading Range Selection Table
. This pin has an internal pull-up resistor.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread
Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal
pull-low resistor.
Spread spectrum clock output.
3
DIV2
I
4
VSS
P
5
SR0
I
6
SSON#
I
7
ModOUT
O
8
VDD
P
Power supply for the entire chip (+3.3V or 5.0V)
Output Frequency Selections
Input Frequency
8 MHz
12 MHz
16 MHz
20 MHz
24 MHz
28 MHz
32 MHz
0 (1/2 X)
4 MHz
6 MHz
8 MHz
10 MHz
12 MHz
14 MHz
16 MHz
DIV2
1 (1X)
8 MHz
12 MHz
16 MHz
20 MHz
24 MHz
28 MHz
32 MHz
Output
Frequency
Frequency Deviation Selections as a Function of Input Frequency
Input Frequency Range
P/N
SR0
8 MHz
12 MHz
16 MHz
20 MHz
24 MHz
28 MHz
32 MHz
Modulation
Rate (KHz)
0
± 3.0%
± 2.5%
± 2.0%
± 1.8%
± 1.5%
± 1.5%
± 1.3%
P2005A
1
± 2.5%
± 2.0%
± 1.8%
± 1.5%
± 1.3%
± 1.3%
± 1.0%
0
± 1.8%
± 1.5%
± 1.2%
± 1.1%
± 0.9%
± 0.9%
± 0.8%
P2005S
1
± 1.5%
± 1.2%
± 1.1%
± 0.9%
± 0.8%
± 0.8%
± 0.6%
(X
IN
/20) * 62.5
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