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參數(shù)資料
| 型號： | P2008A-08TT |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | General Purpose EMI Reduction IC |
| 中文描述： | 32 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | TSSOP-8 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 172K |
| 代理商： | P2008A-08TT |
July 2005
rev 1.3
Spread Spectrum
The
Modulation Output and Spreading Selection Tables
illustrate the two possible spread spectrum options. The optimal
setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a
percentage deviation of the center frequency (Note: The center frequency is the frequency of the external reference input on
XIN/CLKIN, Pin1).
Example:
The P2008A is designed for communications, digital video and imaging applications. It is not only optimized for operation in
the 4MHz – 32MHz range, but its output frequency can be extended down to one half of the input clock frequency using the
divide-by-two feature. This feature extends low frequency as low as to 2MHz. Setting Pin 3 low (DIV2 = 0; Divide-by-two
mode) sets the output frequency (ModOUT) to half the frequency of the input clock (XIN/CLKIN). This is a simple way to
generate a spread spectrum modulated low frequency clock when only a higher frequency signal is available. If you want the
output frequency to be the same as the input, you can either set DIV2=1 or leave it unconnected.
Selecting the P2008A’s spread options is a matter of either setting SR0=1 or SR0=0. Setting SR0=0 set as a lower
modulation spread, while setting it to 1 introduces a wider spectral spread in the output clock.
Refer Modulation output and
Spreading Selections Tables.
The example given in the figure below shows the device set to the divide-by-two mode
(DIV2=0) with a lower spectrum range (SR0=0). The versatility provided by allowing both clock division and spread spectrum
on one chip is already proving to be a popular solution among leading system manufacturers.
P2008A Application Schematic
P2008A
General purpose EMI Reduction IC
3 of 9
Notice: The information in this document is subject to change without notice.
Modulated 4.416MHz is
connected to CLK input
pin of the system
1
2
3
4
XIN/CLKIN
XOUT
DIV2
VSS
SR0
5
6
7
8
SSON#
Mod OUT
VDD
8.832MHz Crystal
+3.3V
0.1μF
P2008A
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