參數(shù)資料
型號: P2681A-08TT
廠商: ALLIANCE SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: General Purpose EMI Reduction IC
中文描述: 20 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝: TSSOP-8
文件頁數(shù): 4/10頁
文件大?。?/td> 471K
代理商: P2681A-08TT
October 2003
rev D
Spread Spectrum Selection
The P2681A performs Zero Cycle Slip when sets at low % spreading. This allows no occurrence of system
timing error. The optimal setting should minimize system EMI to the fullest without affecting system
performance. The spreading is described as a percentage deviation of the center frequency (Note: the center
frequency is the frequency of the external reference input on CLKIN, Pin 1).
P2681A
General Purpose EMI Reduction IC
4 of 10
Notice: The information in this document is subject to change without notice.
Example
: The P2681A is designed for PC peripheral applications. It is not only optimized for operation between
6MHz – 16MHz range, but its output frequency can be extended down to one half of the input clock frequency
using the Divide-by-Two feature. This feature extends low frequency operation to as low as 3MHz. Setting Pin 3
high (
DIV2
=1; Divide-by-Two mode) sets the output frequency (
ModOUT
) to half the frequency of the input clock
(
CLKIN
). This is a simple way to generate a spread spectrum modulated low frequency clock when only a
higher frequency signal is available. If you want the output frequency to be the same as the input, you need to
set
DIV2
=0.
The P2681A’s spread % selection is determined by the external LF value specified in Table 2. Table 1 provides
a particular LF value which allows the % spreading to be selected between +/-0.75% or +/-1.30% by setting SR0
to either 0 and 1. At a specified LF value (See Table 2), SR0 pin allows the user to have the flexibility to digitally
select between large or small % spreading by setting SR0=1 or SR0=0 respectively.
P2681A Application Schematic
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