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| 型號(hào)： | P28F010-65 |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | PROM |
| 英文描述： | 1024K (128K x 8) CMOS FLASH MEMORY |
| 中文描述： | 128K X 8 FLASH 12V PROM, 65 ns, PDIP32 |
| 封裝： | 0.620 X 1.640 INCH, PLASTIC, DIP-32 |
| 文件頁(yè)數(shù)： | 7/30頁(yè) |
| 文件大?。?/td> | 405K |
| 代理商： | P28F010-65 |
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28F010
Table 2. 28F010 Bus Operations
Mode
V
PP(1)
A
0
A
9
CE
Y
OE
Y
WE
Y
DQ
0
–DQ
7
Read
V
PPL
A
0
A
9
V
IL
V
IL
V
IH
Data Out
Output Disable
V
PPL
X
X
V
IL
V
IH
V
IH
Tri-State
READ-ONLY
Standby
V
PPL
X
X
V
IH
X
X
Tri-State
Intelligent Identifier (Mfr)
(2)
V
PPL
V
IL
V
ID(3)
V
ID(3)
V
IL
V
IL
V
IH
Data
e
89H
Data
e
B4H
Intelligent Identifier (Device)
(2)
V
PPL
V
IH
V
IL
V
IL
V
IH
Read
V
PPH
A
0
A
9
V
IL
V
IL
V
IH
Data Out
(4)
READ/WRITE
Output Disable
V
PPH
X
X
V
IL
V
IH
V
IH
Tri-State
Standby
(5)
V
PPH
X
X
V
IH
X
X
Tri-State
Write
V
PPH
A
0
A
9
V
IL
V
IH
V
IL
Data In
(6)
NOTES:
1. Refer to DC Characteristics. When V
PP
e
V
PPL
memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. V
ID
is the Intelligent Identifier high voltage. Refer to DC Characteristics.
4. Read operations with V
PP
e
V
PPH
may access array data or the Intelligent Identifier codes.
5. With V
PP
at high voltage, the standby current equals I
CC
a
I
PP
(standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be V
IL
or V
IH
.
tents of the register default to the read command,
making the 28F010 a read-only memory. In this
mode, the memory contents cannot be altered.
Or, the system designer may choose to ‘‘hardwire’’
V
PP
, making the high voltage supply constantly
available. In this case, all Command Register func-
tions are inhibited whenever V
CC
is below the write
lockout voltage V
LKO
. (See Power Up/Down Protec-
tion) The 28F010 is designed to accommodate ei-
ther design practice, and to encourage optimization
of the processor-memory interface.
The two-step program/erase write sequence to the
Command Register provides additional software
write protections.
BUS OPERATIONS
Read
The 28F010 has two control functions, both of which
must be logically active, to obtain data at the out-
puts. Chip-Enable (CE
Y
) is the power control and
should be used for device selection. Output-Enable
(OE
Y
) is the output control and should be used to
gate data from the output pins, independent of de-
vice selection. Refer to AC read timing waveforms.
When V
PP
is high (V
PPH
), the read operation can be
used to access array data, to output the Intelligent
Identifier codes, and to access data for program/
erase verification. When V
PP
is low (V
PPL
), the read
operation can
only
access the array data.
Output Disable
With OE
Y
at a logic-high level (V
IH
), output from the
device is disabled. Output pins are placed in a high-
impedance state.
Standby
With CE
Y
at a logic-high level, the standby opera-
tion disables most of the 28F010’s circuitry and sub-
stantially reduces device power consumption. The
outputs are placed in a high-impedance state, inde-
pendent of the OE
Y
signal. If the 28F010 is dese-
lected during erasure, programming, or program/
erase verification, the device draws active current
until the operation is terminated.
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manu-
facturer code (89H) and device code (B4H). Pro-
gramming equipment automatically matches the de-
vice with its proper erase and programming algo-
rithms.
7
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相關(guān)代理商/技術(shù)參數(shù) |
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| P28F010-90 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:1024K (128K x 8) CMOS FLASH MEMORY |
| P28F020120 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| P28F020-120 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:28F020 2048K (256K X 8) CMOS FLASH MEMORY |
| P28F020150 | 制造商:Intel 功能描述: |
| P28F020-150 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intel 功能描述: |
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