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Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.07
Freescale Semiconductor
113
2.3.18
PIM Reserved Register
This register is reserved for factory testing of the PIM module and is not available in normal operation.
2.3.19
Port K Data Register (PORTK)
Table 2-16. IRQCR Register Field Descriptions
Field
Description
7
IRQE
IRQ select edge sensitive only
—
Special modes: Read or write anytime.
Normal & emulation modes: Read anytime, write once.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1
and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0 IRQ configured for low level recognition.
6
IRQEN
External IRQ enable
—
Read or write anytime.
1 External IRQ pin is connected to interrupt logic.
0 External IRQ pin is disconnected from interrupt logic.
5-0
Reserved
—
Address 0x001F
Access: User read
1
1
Read: Always reads 0x00
Write: Unimplemented
NOTE
Writing to this register when in special modes can alter the pin functionality.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-16. PIM Reserved Register
Address 0x0032 (PRR)
Access: User read/write
1
7
6
5
4
3
2
1
0
R
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
W
Altern.
Function
ROMCTL
or
EWAIT
ADDR22
mux
NOACC
ADDR21
ADDR20
ADDR19
mux
IQSTAT3
ADDR18
mux
IQSTAT2
ADDR17
mux
IQSTAT1
ADDR16
mux
IQSTAT0
Reset
0
0
0
0
0
0
0
0
Figure 2-17. Port K Data Register (PORTK)