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參數(shù)資料
| 型號： | P4C22-35PMB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ULTRA HIGH SPEED 256 X 4 STATIC CMOS RAM |
| 中文描述： | 超高速靜態(tài)256 × 4 CMOS存儲器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 78K |
| 代理商： | P4C22-35PMB |
3
P4C422
minimum write recovery times by eliminating the “write
recovery glitch.” Reading is performed with chip selct one
(
CS
1
) LOW, chip select two (CS
2
) HIGH, write enable
(
WE
) HIGH and output enable (
OE
) LOW. The informa-
tion stored in the addressed word is read out on the
noninverting outputs (O
through O
). The outputs of the
memory go to an inactive high impedance state whenever
chip select one (
CS
) is HIGH, or during the write
operation when write enable (
WE
) is LOW.
An active LOW write enable (
WE
) controls the writing/
reading operation of the memory. When the chip select
one (
CS
) and the write enable (
WE
) are LOW and the
chip select two (CS
) is HIGH, the information on data
inputs (D
through D
) is written into the addressed
memory word and preconditions the output circuitry so
that true data is present at the outputs when the write
cycle is complete. This preconditioning operation insures
FUNCTIONAL DESCRIPTION
TRUTH TABLE
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V
±
10% except as noted, All Temperature Ranges)
(2)
Mode
Standby
CS
2
L
CS
1
X
WE
X
OE
X
Output
High Z
Standby
X
H
X
X
High Z
D
OUT
Disabled
Read
H
L
X
H
High Z
H
L
H
L
D
OUT
High Z
Write
H
L
L
X
TIMING WAVEFORM OF READ CYCLE
Notes:
H = HIGH
L = Low
X = Don't Care
HIGH Z = Implies outputs are disabled or off. This
condition is defined as high impedance state
for the P4C422.
Sym.
t
RC
t
ACS
t
ZRCS
t
AOS
t
ZROS
t
AA
*V
CC
= 5V
±
5%
Read Cycle Time
(5)
Chip Select Time
(5)
Chip Select to High-Z
(6)
Output Enable Time
Output Enable to High-Z
(6)
Address Access Time
(5)
-10*
Min Max
7.5
8
7.5
8
10
-12
Min
12
Max
8
10
8
10
12
-15
Min
15
Max
8
12
8
12
15
-20
Min
20
Max
12
15
12
15
20
-25
Min
25
Max
15
20
15
20
-35
Min
35
Max
Unit
ns
ns
ns
ns
ns
ns
25
25
30
25
30
35
Parameter
12
ADDRESS
A0–A7
tRC
tAA
tACS
tAOS
tZROS
tZRCS
DATA VALID
CS
1
CS2
OE
WE
DATA
O0–O3
OUTPUTS
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|---|---|
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