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參數(shù)資料
| 型號： | P50N03LDG |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | N-Channel Logic Level Enhancement Mode Field Effect Transistor |
| 中文描述： | N溝道增強(qiáng)模式的邏輯電平場效應(yīng)晶體管 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大小： | 293K |
| 代理商： | P50N03LDG |
2
SEP-22-2004
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P50N03LDG
TO-252 (DPAK)
Lead-Free
NIKO-SEM
On-State Drain Current
1
I
D(ON)
V
DS
= 10V, V
GS
= 10V
50
A
V
GS
= 4.5V, I
D
= 20A
15
18
Drain-Source On-State
Resistance
1
R
DS(ON)
V
GS
= 10V, I
D
= 25A
10
12
m
Forward Transconductance
1
g
fs
V
DS
= 10V, I
D
= 25A
32
S
DYNAMIC
Input Capacitance
C
iss
1200 1800
Output Capacitance
C
oss
600 1000
Reverse Transfer Capacitance
Total Gate Charge
2
Gate-Source Charge
2
Gate-Drain Charge
2
Turn-On Delay Time
2
Rise Time
2
C
rss
V
GS
= 0V, V
DS
= 15V, f = 1MHz
350
500
pF
Q
g
25
50
Q
gs
15
Q
gd
V
DS
= 10V, V
GS
= 10V,
I
D
= 25A
10
nC
t
d(on)
6
16
t
r
V
DS
= 15V, R
L
= 1
120
250
Turn-Off Delay Time
2
t
d(off)
I
D
50A, V
GS
= 10V, R
GEN
= 24
40
90
Fall Time
2
t
f
105
200
nS
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (T
C
= 25 °C)
Continuous Current
Pulsed Current
3
Forward Voltage
1
I
S
50
I
SM
150
A
V
SD
I
S
= 25A, V
GS
= 0V
0.9
1.3
V
Reverse Recovery Time
t
rr
70
nS
Peak Reverse Recovery Current
I
RM(REC)
I
F
= I
S
, dl
F
/dt = 100A /
μ
S
200
A
Reverse Recovery Charge
Q
rr
0.043
μ
C
1
Pulse test : Pulse Width
≤
300
μ
sec, Duty Cycle
≤
2
2
Independent of operating temperature.
3
Pulse width limited by maximum junction temperature.
REMARK: THE PRODUCT MARKED WITH “P50N03LDG”, DATE CODE or LOT #
.
Orders for parts with Lead-Free plating can be placed using the PXXXXXXXG parts name.
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