參數(shù)資料
型號(hào)： P80C51HFP
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： Low voltage 8-bit microcontrollers with UART
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP40
封裝： 0.600 INCH, PLASTIC, SOT-129-1, DIP-40
文件頁(yè)數(shù)： 23/38頁(yè)
文件大?。?/td> 350K
代理商： P80C51HFP
Philips Semiconductors
Product specification
80C51/87C51/80C31
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Jan 20
23
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C, V
CC
= +2.7V to +5.5V, V
SS
= 0V
1, 2, 3
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
14
Oscillator frequency
5
Speed versions :S
3.5
16
MHz
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV4
t
PLAZ
Data Memory
14
ALE pulse width
85
2t
CLCL
–40
t
CLCL
–40
t
CLCL
–30
ns
14
Address valid to ALE low
22
ns
14
Address hold after ALE low
32
ns
14
ALE low to valid instruction in
150
4t
CLCL
–100
ns
14
ALE low to PSEN low
32
t
CLCL
–30
3t
CLCL
–45
ns
14
PSEN pulse width
142
ns
14
PSEN low to valid instruction in
82
3t
CLCL
–105
ns
14
Input instruction hold after PSEN
0
0
ns
14
Input instruction float after PSEN
37
t
CLCL
–25
5t
CLCL
–105
10
ns
14
Address to valid instruction in
207
ns
14
PSEN low to address float
10
ns
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
15, 16
RD pulse width
275
6t
CLCL
–100
6t
CLCL
–100
ns
15, 16
WR pulse width
275
ns
15, 16
RD low to valid data in
147
5t
CLCL
–165
ns
15, 16
Data hold after RD
0
0
ns
15, 16
Data float after RD
65
2t
CLCL
–60
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
ns
15, 16
ALE low to valid data in
350
ns
15, 16
Address to valid data in
397
ns
15, 16
ALE low to RD or WR low
137
239
3t
CLCL
–50
4t
CLCL
–130
t
CLCL
–50
t
CLCL
–50
7t
CLCL
–150
ns
15, 16
Address valid to WR low or RD low
122
ns
15, 16
Data valid to WR transition
13
ns
15, 16
Data hold after WR
13
ns
16
Data valid to WR high
287
ns
15, 16
RD low to address float
0
0
ns
15, 16
RD or WR high to ALE high
23
103
t
CLCL
–40
t
CLCL
+40
ns
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift Register
18
High time
20
20
t
CLCL
–t
CLCX
t
CLCL
–t
CHCX
20
ns
18
Low time
20
20
ns
18
Rise time
20
ns
18
Fall time
20
20
ns
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 8XC51 and 80C31 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.
4. See application note AN457 for external memory interface.
5. Parts are guaranteed to operate down to 0Hz.
17
Serial port clock cycle time
750
12t
CLCL
10t
CLCL
–133
2t
CLCL
–117
0
ns
17
Output data setup to clock rising edge
492
ns
17
Output data hold after clock rising edge
8
ns
17
Input data hold after clock rising edge
0
ns
17
Clock rising edge to input data valid
492
10t
CLCL
–133
ns
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