參數(shù)資料
型號(hào)： P80C51SBAA
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, MO-047, SOT187-2, LCC-44
文件頁(yè)數(shù)： 24/38頁(yè)
文件大?。?/td> 350K
代理商： P80C51SBAA
Philips Semiconductors
Product specification
80C51/87C51/80C31
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Jan 20
24
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C, V
CC
= 5V
±
10%, V
SS
= 0V
1, 2, 3
VARIABLE CLOCK
4
16MHz to f
max
MIN
2t
CLCL
–40
t
CLCL
–25
t
CLCL
–25
33
MIN
21
5
Hz CLOCK
SYMBOL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift Register
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 8XC51 and 80C31 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.
4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz
“AC Electrical Characteristics”, page 23.
5. Parts are guaranteed to operate down to 0Hz.
FIGURE
14
14
14
14
14
14
14
14
14
14
14
PARAMETER
MAX
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
4t
CLCL
–65
55
t
CLCL
–25
3t
CLCL
–45
5
45
3t
CLCL
–60
30
0
0
t
CLCL
–25
5t
CLCL
–80
10
5
70
10
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
16
15, 16
15, 16
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
6t
CLCL
–100
6t
CLCL
–100
82
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5t
CLCL
–90
60
0
0
2t
CLCL
–28
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
32
90
105
140
3t
CLCL
–50
4t
CLCL
–75
t
CLCL
–30
t
CLCL
–25
7t
CLCL
–130
40
45
0
5
80
0
0
55
t
CLCL
–25
t
CLCL
+25
5
18
18
18
18
High time
Low time
Rise time
Fall time
0.38t
CLCL
0.38t
CLCL
t
CLCL
–t
CLCX
t
CLCL
–t
CHCX
5
5
ns
ns
ns
ns
17
17
17
17
17
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
12t
CLCL
10t
CLCL
–133
2t
CLCL
–80
0
360
167
ns
ns
ns
ns
ns
0
10t
CLCL
–133
167
相關(guān)PDF資料
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