參數(shù)資料
型號(hào): P80CL31
廠商: NXP Semiconductors N.V.
英文描述: Low voltage 8-bit microcontrollers with UART
中文描述: 低電壓的8位微控制器的UART的
文件頁數(shù): 54/68頁
文件大小: 305K
代理商: P80CL31
1997 Apr 15
54
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART
P80CL31; P80CL51
23 AC CHARACTERISTICS
V
DD
= 5 V; V
SS
= 0 V; T
amb
=
40 to +85
°
C; C
L
= 50 pF for Port 0, ALE and PSEN; C
L
= 40 pF for all other outputs
unless specified; t
CLK
= 1/ f
CLK
.
SYMBOL
PARAMETER
f
osc
= 12 MHz
f
osc
= VARIABLE
UNIT
MIN.
MAX.
MIN.
MAX.
Program Memory
(Fig.32)
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
PXAV
t
AVIV
t
PLAZ
ALE pulse width
address valid to ALE LOW
address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
PSEN pulse width
PSEN LOW to valid instruction in
input instruction hold after PSEN
input instruction float after PSEN
PSEN to address valid
address to valid instruction in
PSEN LOW to address float
127
43
48
58
215
0
75
12
233
125
63
302
2t
CLK
40
t
CLK
40
t
CLK
35
t
CLK
25
3t
CLK
35
0
t
CLK
8
0
4t
CLK
100
3t
CLK
125
t
CLK
20
5t
CLK
115
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
External Data Memory
(Figs 33 and 34)
t
RLRH
t
WLWH
t
LLAX
t
RLDV
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
WHLH
t
QVWX
t
QVWH
t
WHQX
t
RLAZ
RD pulse width
WR pulse width
address hold after ALE LOW
RD LOW to valid data in
data float after RD
ALE LOW to valid data in
address to valid data in
ALE LOW to RD or WR LOW
address valid to RD or WR LOW
RD or WR HIGH to ALE HIGH
data valid to WR transition
data valid time WR HIGH
data hold after WR
RD LOW to address float
400
400
48
200
203
43
23
433
33
150
97
517
585
300
123
12
6t
CLK
100
6t
CLK
100
t
CLK
35
5t
CLK
165
2t
CLK
70
8t
CLK
150
9t
CLK
165
3t
CLK
+ 50
t
CLK
+ 40
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3t
CLK
50
4
t
CLK
40
t
CLK
60
7t
CLK
150
t
CLK
50
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