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參數(shù)資料
| 型號： | P80CL410HFP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 8-bit microcontrollers with I2C-bus |
| 中文描述： | 8-BIT, 12 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 10/60頁 |
| 文件大?。?/td> | 266K |
| 代理商： | P80CL410HFP |
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1997 Apr 10
10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I
2
C-bus
P80CL410; P83CL410
8
FUNCTIONAL DESCRIPTION OVERVIEW
This chapter gives a brief overview of the device.
The detailed functional description is in the following
chapters:
Chapter 9 “Memory organization”
Chapter 10 “I/O facilities”
Chapter 11 “Timers/event counters”
Chapter 12 “Reduced power modes”
Chapter 13 “I
2
C-bus serial I/O”
Chapter 14 “Interrupt system”
Chapter 15 “Oscillator circuitry”
Chapter 16 “Reset”.
8.1
General
The P8xCL410 is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications
such as instrumentation, industrial control, intelligent
computer peripherals and consumer products.
The device provides hardware features, architectural
enhancements and new instructions to function as a
controller for applications requiring up to 64 kbytes of
Program Memory and/or up to 64 kbytes of Data Memory.
The P8xCL410 contains a 4 kbytes Program Memory
(ROM; P83CL410); a static 128 bytes Data Memory
(RAM); 32 I/O lines; two16-bit timer/event counters;
a thirteen-source, two priority-level, nested interrupt
structure and on-chip oscillator and timing circuit.
An I
2
C-bus serial interface is also provided.
The device has two software-selectable modes of reduced
activity for power reduction:
Idle mode
; freezes the CPU while allowing the timers,
serial I/O and interrupt system to continue functioning.
Power-down mode
; saves the RAM contents but
freezes the oscillator causing all other chip functions to
be inoperative.
8.2
CPU timing
A machine cycle consists of a sequence of 6 states. Each
state lasts for two oscillator periods, thus a machine cycle
takes 12 oscillator periods or 1
μ
s if the oscillator
frequency (f
osc
) is 12 MHz.
9
MEMORY ORGANIZATION
The P8xCL410 has 4 kbytes of Program Memory (ROM;
P83CL410 only) plus 128 bytes of Data Memory (RAM) on
board. The device has separate address spaces for
Program and Data Memory (see Fig.5). Using Port latches
P0 and P2, the P8xCL410 can address a maximum of
64 kbytes of program memory and a maximum of
64 kbytes of data memory. The CPU generates. The CPU
generates both read (RD) and write (WR) signals for
external Data Memory accesses, and the read strobe
(PSEN) for external Program Memory.
9.1
Program Memory
After reset the CPU begins program execution at location
0000H. The lower 4 kbytes of Program Memory can be
implemented in the on-chip ROM (P83CL410 only) or in
external Program Memory.
If the EA pin is tied to V
DD
, then Program Memory fetches
from addresses 0000H to 0FFFH are directed to the
internal ROM. Fetches from addresses 1000H to FFFFH
are directed to external ROM. Program Counter values
greater than 0FFFH are automatically addressed to
external memory regardless of the state of the EA pin.
9.2
Data Memory
The P8xCL410 contains128 bytes of internal RAM and 27
Special Function Registers (SFR). The memory map
(Fig.5) shows the internal Data Memory space divided into
the lower 128, the upper 128, and the SFR space.
The lower 128 bytes of the internal RAM are organized as
mapped in Fig.6. The lowest 32 bytes are grouped into 4
banks of 8 registers. Program instructions refer to these
registers within a register bank as R0 through R7. Two bits
in the Program Status Word select which register bank is
in use. The next 16 bytes above the register banks form a
block of bit-addressable memory space. The 128 bits in
this area can be directly addressed by the single-bit
manipulation instructions. The remaining registers
(30H to 7FH) are directly and indirectly byte addressable.
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