參數(shù)資料
型號： P83C270
廠商： NXP Semiconductors N.V.
英文描述： Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC)(在NTSC TV中應(yīng)用的具有屏幕顯示和字幕關(guān)閉特點(diǎn)的微控制器)
中文描述： 微控制器用于NTSC電視的屏幕顯示（OSD）和字幕（CC）的（在NTSC電視中應(yīng)用的具有屏幕顯示和字幕關(guān)閉特點(diǎn)的微控制器）
文件頁數(shù)： 23/80頁
文件大?。?/td> 266K
代理商： P83C270
1999 Jun 11
23
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
P8xCx70 family
11.3
Interrupt priority structure
Each interrupt source can be assigned one of two priority
levels. Interrupt priority levels are defined by the Interrupt
Priority Registers (IP0 and IP1). These registers are
described in Sections 11.3.1 and 11.3.2.
A low priority interrupt may be interrupted by a high priority
interrupt level interrupt. A high priority interrupt routine
cannot be interrupted by any other interrupt source. If two
interrupts of different priority occur simultaneously, the
high priority level request is serviced. If requests of the
same priority are received simultaneously, an internal
polling sequence determines which request is serviced.
Thus, within each priority level, there is a second priority
structure determined by the polling sequence. This second
priority structure is shown in Table 25.
Table 25
Interrupt priority
Note
1.
The ‘priority within level’ structure is only used to
resolve simultaneous requests of the same priority
level.
SOURCE
PRIORITY WITHIN LEVEL
(1)
INT0
I
2
C-bus
Timer 0
INT1
BUSY
Timer 1
CC
highest
↓
↓
↓
↓
↓
lowest
11.3.1
I
NTERRUPT
P
RIORITY
R
EGISTER
0 (IP0)
Table 26
Interrupt Priority Register 0 (SFR address B8H)
Table 27
Description of IP0 bits
Note
1.
Where: logic 0 = low priority; logic 1 = high priority.
7
6
5
4
3
2
1
0
PS1
PT1
PX1
PT0
PX0
BIT
(1)
SYMBOL
PS1
PT1
PX1
PT0
PX0
DESCRIPTION
7 to 6
5
4
3
2
1
0
This bit is not used, program to a logic 0 for future compatibility reasons.
I
2
C-bus SIO interrupt priority level.
This bit is not used, program to a logic 0 for future compatibility reasons.
Timer 1 interrupt priority level.
External interrupt 1 priority level.
Timer 0 interrupt priority level.
External interrupt 0 priority level.
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