參數(shù)資料
型號(hào)： P83C562EHA
廠商： NXP Semiconductors N.V.
元件分類： 8位微控制器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁(yè)數(shù)： 23/52頁(yè)
文件大小： 299K
代理商： P83C562EHA
1997 Apr 08
23
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
12.3
Watchdog Timer (T3)
In addition to Timer T2 and the standard timers, a
Watchdog Timer is also available, consisting of an 11-bit
prescaler and a 8-bit timer. The functional diagram of the
Watchdog Timer is shown in Fig.11. The timer is
incremented every t seconds,
where:
When a timer overflow occurs, the microcontroller is reset
and a reset output pulse is generated at the RST pin.
To prevent a system reset the timer must be reloaded in
time by the application software. If the processor suffers a
hardware/ software malfunction, the software will fail to
reload the timer. This failure will produce a reset upon
overflow thus preventing the processor running out of
control.
t
12
2048
f
OSC
×
=
The Watchdog Timer can only be reloaded if the condition
flag WLE in the Power Control Register has been
previously set by software. At the moment the counter is
loaded the condition flag is automatically cleared.
The timer interval between the timer's reloading and
occurrence of a reset, is dependent upon the reloaded
value. For example, this may range from 2 ms to 0.5 s
when using an oscillator frequency of 12 MHz. In the Idle
state the Watchdog Timer and reset circuitry remain
active.
The Watchdog Timer is controlled by the Enable
Watchdog pin (EW). A logic 0 enables the Watchdog
Timer and disables the Power-down mode. A logic 1
disables the Watchdog Timer and enables the
Power-down mode.
Fig.11 Functional diagram of Watchdog Timer.
handbook, full pagewidth
MBC753
INTERNAL BUS
write
T3
PRESCALER
11-BIT
CLEAR
TIMER T3 (8-BIT)
LOAD
overflow
internal
reset
LOADEN
EW
LOADEN
PCON.4
PCON.1
CLEAR
WLE
PD
RRST
RST
P
VDD
INTERNAL BUS
f
/12
osc
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