參數(shù)資料
型號(hào)： P83C566
廠商： NXP Semiconductors N.V.
英文描述： Microcontrollers for PAL/SECAM TV with OSD and VST
中文描述： 微控制器對(duì)于PAL / SECAM電視的OSD和偉仕
文件頁(yè)數(shù)： 29/92頁(yè)
文件大?。?/td> 382K
代理商： P83C566
1999 Mar 10
29
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
11.10 VSYNC interrupt and level status bit
The SFR VINT is read-only. Figure 13 shows the timing diagram of VSYNC interrupt.
Table 33
VSYNC Interrupt Register (SFR address C9H)
Table 34
Description of VINT bits
11.10.1 E
XTERNAL INTERRUPT REQUEST
(IQ7)
A rising or falling edge (see Fig.13) of the active VSYNC signal generates a pending interrupt to the CPU and drives IQ7
HIGH (IQ7 resides in the SFR IRQ1). In the service routine, this bit should be cleared before return to main routine.
As long as this bit is HIGH a pending interrupt is always there. Each time VSYNC is activated by a rising or falling edge,
IQ7 is set HIGH. If the interrupt is not serviced before the next leading VSYNC edge, then IQ7 is written HIGH again and
no error of overrun is indicated.
7
6
5
4
3
2
1
0
VLVL
BIT
SYMBOL
VLVL
DESCRIPTION
7 to 1
0
These 7 bits are not used.
VSYNC input pin level.
The state of this bit indicates the level of the VSYNC input. As
the input polarity of VSYNC is programmable two situations may be defined.
If VSYNC is programmed active HIGH then:
VLVL = 0, means VSYNC is at a LOW level, i.e. raster scan period
VLVL = 1, means VSYNC is at HIGH level, i.e.vertical fly-back period.
If VSYNC is programmed to active LOW then:
VLVL = 0, means VSYNC is at LOW level, i.e. vertical fly-back period
VLVL = 1, means VSYNC is at HIGH level, i.e. raster scan period
Fig.13 Timing diagram of VSYNC interrupt.
handbook, full pagewidth
VSYNC
VSYNC
VSYNC active LOW (Vp = 0)
VSYNC active HIGH (Vp = 1)
MGL286
The falling edge of VSYNC generates interrupt
The rising edge of VSYNC generates an interrupt
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