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參數資料
| 型號： | P83C834CFP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontrollers with LCD-driver |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數： | 11/36頁 |
| 文件大小： | 165K |
| 代理商： | P83C834CFP |
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1997 Jul 03
11
Philips Semiconductors
Product specification
8-bit microcontrollers with LCD-driver
P83C434; P83C834
6.3
Interrupts
The P83C434 and P83C834 have 4 interrupt sources;
these are shown Fig.10.
Interrupt INT0 is generated when one of the I/O lines
(P0.0 to P0.3) becomes LOW; or one of I/O lines
(P0.4 to P0.7) equals the corresponding bit in the MCON
register (ILVL0 to ILVL3). By means of bit IT0 in the TCON
register this interrupt can be chosen to be:
Level sensitive, when IT0 = LOW; INT0 must be inactive
before a return from interrupt is given, otherwise the
same interrupt will occur again.
Edge sensitive, when IT0 = HIGH; the internal hardware
will reset the latch when the LCALL is executed for the
vector address (see Table 7).
Interrupt INT1 is generated by the overflow of the 1-second
counter. The overflow signal is latched. The output of the
latch will set the SECINT bit in the MCON register.
When SECINT is set the overflow latch will be reset.
Interrupt INT1 is selected as edge or level sensitive by the
state of the IT1 bit in the TCON register. However, it is
recommended to always set IT1 to HIGH (edge sensitive)
so that IE1 will be reset by the internal hardware when the
LCALL is executed for the vector address.
In the interrupt routine SECINT should be reset by
software so that with the next 1-second overflow another
interrupt may be generated.
Timer 0 and Timer 1 interrupts are generated by TF0 and
TF1 which are set by an overflow of their respective
Timer/Counter registers (except for Timer 0 in mode 3;
see “Data Handbook IC20, 80C51 Family, Chapter
Timer/Counters”). When a timer interrupt is generated, the
flag that generated it is cleared by the internal hardware
when the LCALL is executed for the vector address.
All of the bits that generate interrupts can be set or cleared
by software, with the same result as though it had been set
or cleared by hardware. That is, interrupts can be
generated or pending interrupts can be cancelled in
software.
Each of these interrupts sources can be individually
enabled or disabled by setting or clearing the bit in Special
Function Register IE (see Table 5). IE also contains a
global disable bit EA, which disables all interrupts at once.
6.3.1
I
NTERRUPT
E
NABLE
R
EGISTER
(IE)
Table 4
Interrupt Enable Register (address A8H)
Table 5
Description of IE bits
7
6
5
4
3
2
1
0
EA
ET1
EX1
ET0
EX0
BIT
SYMBOL
DESCRIPTION
7
EA
Disable all interrupts
. If EA is:
LOW, then no interrupt will be acknowledged.
HIGH, then each interrupt source is individually enabled or disabled by setting or
clearing its enable bit.
Reserved.
Enables or disables the Timer 1 Overflow Interrupt
. If ET1 is LOW then the Timer 1
interrupt is disabled.
Enables or disables the External Interrupt 1
. If EX1 is LOW then the External 1
interrupt is disabled.
Enables or disables the Timer 0 Overflow Interrupt
. If ET0 is LOW then the Timer 0
interrupt is disabled.
Enables or disables the External Interrupt 0
. If EX0 is LOW then the External 0
interrupt is disabled.
6 to 4
3
ET1
2
EX1
1
ET0
0
EX0
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