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參數(shù)資料
| 型號： | P83CL410 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage 8-bit microcontrollers with I2C-bus |
| 中文描述： | 低電壓的8位微控制器帶有I2C總線 |
| 文件頁數(shù)： | 14/60頁 |
| 文件大?。?/td> | 266K |
| 代理商： | P83CL410 |
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1997 Apr 10
14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
I
2
C-bus
P80CL410; P83CL410
10 I/O FACILITIES
10.1
Ports
The P8xCL410 has 32 I/O lines treated as 32 individually
addressable bits or as four parallel 8-bit addressable ports.
Ports 0, 1, 2 and 3 perform the alternative functions
detailed below. To enable a port pin alternate function, the
port bit latch in its SFR must contain a logic 1.
Port 0 Provides the multiplexed low-order address and
data bus for expanding the device with standard
memories and peripherals.
Port 1 Used for the external interrupts INT2 to INT9, and
the I
2
C-bus interface lines SCL and SDA.
Port 2 Provides the high-order address when expanding
the device with external Program or Data Memory.
Port 3 Pins can be configured individually to provide:
External interrupt request inputs: INT1 and INT0
Timer/counter inputs: T1 and T0
Control signals to read and write to external
memories: RD and WR.
Each port consists of a latch (SFRs P0 to P3), an output
driver and input buffer. Ports 1, 2, and 3 have internal
pull-ups Figure 8(a) shows that the strong transistor ‘p1’ is
turned on for only 2 oscillator periods after a LOW-to-HIGH
transition in the port latch. When on, it turns on ‘p3’ (a weak
pull-up) through the inverter. This inverter and ‘p3’ form a
latch which holds the logic 1. In Port 0 the pull-up ‘p1’ is
only on when emitting logic 1s for external memory
access. Writing a logic 1 to a Port 0 bit latch leaves both
output transistors switched off so that the pin can be used
as a high-impedance input.
10.2
Port options
The pins of port 1 (except P1.6 and P1.7; with option 2S
only), port 2 and port 3 may be individually configured with
one of the following options. These options are also shown
in Fig.8.
Option 1
Standard Port
; quasi-bidirectional I/O with
pull-up. The strong booster pull-up ‘p1’ is turned
on for two oscillator periods after a
LOW-to-HIGH transition in the port latch;
Fig.8(a).
Option 2
Open-drain
; quasi-bidirectional I/O with
n-channel open-drain output. Use as an output
requires the connection of an external pull-up
resistor; see Fig.8(b).
Option 3
Push-pull
; output with drive capability in both
polarities. Under this option, pins can only be
used as outputs; see Fig.8(c).
10.3
Port 0 options
The definition of port options for Port 0 is slightly different.
Two cases are considered. First, access to external
memory (EA = 0 or access above the built-in memory
boundary) and second, I/O accesses.
10.3.1
E
XTERNAL MEMORY ACCESSES
Option 1 True logic 0 and logic 1 are written as address to
the external memory (strong pull-up to be used).
Option 2 An external pull-up resistor is required for
external accesses.
Option 3 Not allowed for external memory accesses as
the port can only be used as output.
10.3.2
I/O A
CCESSES
Option 1 When writing a logic 1 to the port latch, the
strong pull-up ‘p1’ will be on for 2 oscillator
periods. No weak pull-up exists. Without an
external pull-up, this option can be used as a
high-impedance input.
Option 2 Open-drain; quasi-directional I/O with n-channel
open-drain output. Use as an output requires the
connection of an external pull-up resistor.
See Fig.8(b).
Option 3 Push-Pull; output with drive capability in both
polarities. Under this option pins can only be
used as outputs. See Fig.8(c).
10.4
SET/RESET options
Individual mask selection of the post-reset state is
available with any of the above pins. The required
selection is made by appending ‘S’ or ‘R’ to Options 1, 2,
or 3 above.
Option R RESET, at reset this pin will be initialized LOW.
Option S SET, at reset this pin will be initialized HIGH.
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