參數(shù)資料
型號: P87C51UFBB
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz
中文描述: 8-BIT, OTPROM, 33 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù): 21/34頁
文件大?。?/td> 394K
代理商: P87C51UFBB
2001 Apr 06
21
Philips Semiconductors
Preliminary specification
P87C51MB2/P87C51MC2
80C51 8-bit microcontroller family with extended memory
64KB/96KB OTP with 2KB/3KB RAM
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0 to +70°C for commercial unless otherwise specified.
1,2,3
SYMBOL FIGURE(S)
PARAMETER
2.7V < VDD < 5.5V
4.5V < VDD < 5.5V
UNIT
Variable Clock
4
f
OSC
=12MHz
4
MIN
Variable Clock
4
f
OSC
=24MHz
4
MIN
MIN
0
MAX
12
MAX
MIN
0
MAX
24
MAX
f
OSC
t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
Oscillator frequency
MHz
15
CLock cycle
83
41.5
ns
1,2
ALE pulse width
t
CLCL
-66
t
CHCX
-25
t
CLCX
-25
16
t
CLCL
-33
t
CHCX
-12
t
CLCX
-12
8
ns
1,2,3, 4,5,6 Address valid to ALE low
8
4
ns
1,2,3, 4,5,6 Address hold after ALE low
8
4
ns
1,2
ALE low to valid instruction in
2t
CLCL
-108
58
2t
CLCL
-54
29
ns
1,2
ALE low to PSEN low
t
CLCX
-25
t
CLCL
+t
CHCX
-66
8
t
CLCX
-12
t
CLCL
+t
CHCX
-33
4
ns
t
PLPH
1,2
PSEN pulse width
50
25
ns
t
PLIV
1,2
PSEN low to valid instruction in
t
CLCL
+t
CHCX
-91
25
t
CLCL
+t
CHCX
-46
12
ns
t
PXIX
t
PXIZ
1,2
Input instruction hold after PSEN
0
0
0
0
ns
1,2
Input instruction float after PSEN
t
CLCX
-25
2t
CLCL
+t
CHCX
-36
t
CLCL
+t
CHCX
-44
16
8
t
CLCX
-12
2t
CLCL
+t
CHCX
-28
2t
CLCL
+t
CHCX
-34
8
4
ns
t
AVIV
1
Address (A8-A15) to valid instruction
in (non-Extended Addressing Mode)
180
81
ns
t
AVIV1
2
Address (A8-A15) to valid instruction
in (Extended Addressing Mode)
89
33
ns
t
PLAZ
1,2
PSEN low to address float
16
8
ns
Data Memory
t
RLRH
t
WLWH
3,4
RD pulse width
3t
CLCL
-166
3t
CLCL
-166
83
3t
CLCL
-83
3t
CLCL
-83
41.5
ns
5,6
WR pulse width
83
41.5
ns
t
RLDV
3,4
RD low to valid data in
2t
CLCL
+t
CHCX
-141
58
2t
CLCL
+t
CHCX
-70
29
ns
t
RHDX
t
RHDZ
t
LLDV
3,4
Data hold after RD
0
0
0
0
ns
3,4
Data float after RD
t
CLCL
-34
4t
CLCL
-250
4t
CLCL
+t
CHCX
-36
3t
CLCL
+t
CHCX
-44
t
CLCL
+t
CLCX
+83
49
t
CLCL
-17
4t
CLCL
-125
4t
CLCL
+t
CHCX
-28
3t
CLCL
+t
CHCX
-34
t
CLCL
+t
CLCX
+41
24
ns
3,4
ALE low to valid data in
83
41
ns
t
AVDV
3
Address (A8-A15) to valid data in
(non-Extended Addressing Mode)
346
164
ns
t
AVDV1
4
Address (A8-A15) to valid data in
(Extended Addressing Mode)
255
116
ns
t
LLWL
3,4, 5,6
ALE low to RD or WR low
t
CLCL
+t
CLCX
-83
208
t
CLCL
+t
CLCX
-41
104
ns
t
AVWL
3,5
Address (A8-A15) valid to WR or RD
low (non-Extended Addressing
Mode)
Address (A8-A15) valid to WR or RD
low (Extended Addressing Mode)
Data valid to WR transition
2t
CLCL
-15
151
2t
CLCL
-20
63
ns
t
AVWL1
4,6
t
CLCL
-20
63
t
CLCL
-25
16.5
ns
t
QVWX
t
WHQX
5,6
t
CLCX
-33
t
CHCX
-24
3t
CLCL
+t
CLCX
0
t
CLCX
-16
t
CHCX
-11
3t
CLCL
+t
CLCX
0
ns
5,6
Data hold after WR
9
5
ns
t
QVWH
5,6
Data valid to WR high
75
37.5
ns
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
3,4
RD low to address float
0
0
0
0
ns
3,4, 5,6
RD or WR high to ALE high
t
CHCX
-24
t
CHCX
+25
9
75
t
CHCX
-11
t
CHCX
+12
5
37
ns
12
High time
33
t
CLCL
-t
CLCX
t
CLCL
-t
CHCX
8
33
50
16
t
CLCL
-t
CLCX
t
CLCL
-t
CHCX
4
16
24.5
ns
12
Low time
33
33
50
16
16
24.5
ns
12
Rise time
8
4
ns
12
Fall Time
8
8
4
4
ns
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