參數(shù)資料
型號： P87C52X2
廠商： NXP Semiconductors N.V.
英文描述： 80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP 128B/256B RAM low voltage 2.7 to 5.5 V, low power, high speed 30/33 MHz
中文描述： 80C51的8位單片機系列4K/8K/16K/32K的ROM / RAM的檢察官辦公室128B/256B低電壓2.7至5.5 V，低功耗，高速33分之30兆赫
文件頁數(shù)： 38/56頁
文件大?。?/td> 337K
代理商： P87C52X2
Philips Semiconductors
Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
1999 Apr 01
38
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C, V
CC
= +2.7V to +5.5V, V
SS
= 0V
1, 2, 3
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
29
Oscillator frequency
5
Speed versions : 4; 5;S
3.5
16
MHz
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV5
t
PLAZ
Data Memory
29
ALE pulse width
85
2t
CLCL
–40
t
CLCL
–40
t
CLCL
–30
ns
29
Address valid to ALE low
22
ns
29
Address hold after ALE low
32
ns
29
ALE low to valid instruction in
150
4t
CLCL
–100
ns
29
ALE low to PSEN low
32
t
CLCL
–30
3t
CLCL
–45
ns
29
PSEN pulse width
142
ns
29
PSEN low to valid instruction in
82
3t
CLCL
–105
ns
29
Input instruction hold after PSEN
0
0
ns
29
Input instruction float after PSEN
37
t
CLCL
–25
5t
CLCL
–105
10
ns
29
Address to valid instruction in
207
ns
29
PSEN low to address float
10
ns
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
30, 31
RD pulse width
275
6t
CLCL
–100
6t
CLCL
–100
ns
30, 31
WR pulse width
275
ns
30, 31
RD low to valid data in
147
5t
CLCL
–165
ns
30, 31
Data hold after RD
0
0
ns
30, 31
Data float after RD
65
2t
CLCL
–60
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
ns
30, 31
ALE low to valid data in
350
ns
30, 31
Address to valid data in
397
ns
30, 31
ALE low to RD or WR low
137
239
3t
CLCL
–50
4t
CLCL
–130
t
CLCL
–50
t
CLCL
–50
7t
CLCL
–150
ns
30, 31
Address valid to WR low or RD low
122
ns
30, 31
Data valid to WR transition
13
ns
30, 31
Data hold after WR
13
ns
31
Data valid to WR high
287
ns
30, 31
RD low to address float
0
0
ns
30, 31
RD or WR high to ALE high
23
103
t
CLCL
–40
t
CLCL
+40
ns
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift Register
33
High time
20
20
t
CLCL
–t
CLCX
t
CLCL
–t
CHCX
20
ns
33
Low time
20
20
ns
33
Rise time
20
ns
33
Fall time
20
20
ns
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. See application note AN457 for external memory interface.
5. Parts are guaranteed to operate down to 0Hz.
32
Serial port clock cycle time
750
12t
CLCL
10t
CLCL
–133
2t
CLCL
–117
0
ns
32
Output data setup to clock rising edge
492
ns
32
Output data hold after clock rising edge
8
ns
32
Input data hold after clock rising edge
0
ns
32
Clock rising edge to input data valid
492
10t
CLCL
–133
ns
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