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參數(shù)資料
| 型號(hào)： | P87C591VFB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 27 PF 5% 50V NPO/COG (0805) CHIP CAP TR |
| 中文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 X 1.75 MM, PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 131/161頁(yè) |
| 文件大小： | 588K |
| 代理商： | P87C591VFB |
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1999 Aug 19
131
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
21 INTERRUPTS
The 8xC591 has fifteen interrupt sources, each of which
can be assigned one of four priority levels. The five
interrupt sources common to the 80C51 are the external
interrupts (INT0 and INT1), the timer 0 and timer 1
interrupts (lT0 and IT1), and the serial I/O interrupt (RI or
TI). In the 8xC591, the standard serial interrupt is called
SIO0.
The seven Timer T2 interrupts are generated by flags
CTl0-CTI3, CMl0-CMl1, and by the logical OR of flags
T2OV and T2BO. Flags CTl0 to CTI3 are set by input
signals CT0l to CT3I. The inputs INT2 to INT5 can be
regarded as 4 additional external interrupts, if the capture
facility of Timer T2 is not used (details see Timer T2 in
Section 16.1.4.1).
Flags CMl0 to CMl1 are set when a match occurs between
Timer T2 and the compare registers CM0 and CM1. When
an 8-bit or 16-bit overflow occurs, flags T2BO and T2OV
are set, respectively. These eight flags are not cleared by
hardware and must be reset by software to avoid recurring
interrupts.
The ADC interrupt is generated by the ADCl flag in the
ADC control register (ADCON). This flag is set when an
ADC conversion result is ready to be read. ADCl is not
cleared by hardware and must be reset by software to
avoid recurring interrupts. The SIO1 (I
2
C) interrupt is
generated by the SI flag in the SI01 control register
(S1CON). This flag is set when S1STA is loaded with a
valid status code.
The ADCl flag may be reset by software. It cannot be set
by software. All other flags that generate interrupts may be
set or cleared by software, and the effect is the same as
setting or resetting the flags by hardware. Thus, interrupts
may be generated by software and pending interrupts can
be cancelled by software.
A CAN interrupt is generated (vector address 006BH)
when one or more bits of CANCON register are set (refer
to CAN Section 12.5.5 Interrupt Register (IR) for details).
21.1
Interrupt Enable Registers
Each interrupt source can be individually enabled or
disabled by setting or clearing a bit in the interrupt enable
Special Function Registers lENO and lEN1. All interrupt
sources can also be globally enabled or disabled by setting
or clearing bit EA in lENO. The interrupt enable registers
are described in Section 21.2.1 and 21.2.2).
There are 3 SFRs associated with each of the four-level
interrupts. They are the lENx, lPx, and lPxH (see
Section 21.2.3 to 21.2.6). The lPxH (Interrupt Priority
High) register makes the four-level interrupt structure
possible.
The function of the lPxH SFR is simple and when
combined with the lPx SFR determines the priority of each
interrupt. The priority of each interrupt is determined as
shown in the following table:
Table 92
The priority scheme for servicing the interrupts is the same
as that for the 80C51, except there are four interrupt levels
rather than two as on the 80C51. An interrupt will be
serviced as long as an interrupt of equal or higher priority
is not already being serviced. If an interrupt of equal or
higher level priority is being serviced, the new interrupt will
wait until it is finished before being serviced. If a lower
priority level interrupt is being serviced, it will be stopped
and the new interrupt serviced. When the new interrupt is
finished, the lower priority level interrupt that was stopped
will be completed.
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPxH.x
IPx.x
0
0
1
1
0
1
0
1
Level 0 (lowest priority)
Level 1
Level 2
Level 3 (highest priority)
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