參數(shù)資料
型號: P87C660X2
英文描述: 80C51 8-bit microcontroller family 16KB OTP/ROM. 512B RAM low voltage (2.7 to 5.5 V). low power. high speed (30/33 MHZ). two 400KB I2C interfaces
中文描述: 80C51的8位單片機系列16KB的檢察官辦公室/光盤。 512B RAM的低電壓(2.7至5.5 V)。低功耗。高速(三十三分之三十兆赫)。 2 400KB I2C接口
文件頁數(shù): 51/102頁
文件大?。?/td> 568K
代理商: P87C660X2
Philips Semiconductors
Product data
P8xC660X2/661X2
80C51 8-bit microcontroller family
16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
2
C interfaces
2003 Oct 02
51
S
08H
SLA
W
A
DATA
A
S
BOTH MASTERS CONTINUE
WITH SLA TRANSMISSION
18H
28H
OTHER MASTER SENDS REPEATED
START CONDITION EARLIER
SU00975
Figure 26. Simultaneous Repeated START Conditions from 2 Masters
STA FLAG
TIME OUT
SDA LINE
SCL LINE
START CONDITION
SU00976
Figure 27. Forced Access to a Busy I
2
C Bus
I
2
C B
US
O
BSTRUCTED
BY
A
L
OW
L
EVEL
ON
SCL
OR
SDA
An I
2
C bus hang-up occurs if SDA or SCL is pulled LOW by an
uncontrolled source. If the SCL line is obstructed (pulled LOW) by a
device on the bus, no further serial transfer is possible, and the
SIO1 hardware cannot resolve this type of problem. When this
occurs, the problem must be resolved by the device that is pulling
the SCL bus line LOW.
If the SDA line is obstructed by another device on the bus (e.g., a
slave device out of bit synchronization), the problem can be solved
by transmitting additional clock pulses on the SCL line (see Figure
28). The SIO1 hardware transmits additional clock pulses when the
STA flag is set, but no START condition can be generated because
the SDA line is pulled LOW while the I
2
C bus is considered free.
The SIO1 hardware attempts to generate a START condition after
every two additional clock pulses on the SCL line. When the SDA
line is eventually released, a normal START condition is transmitted,
state 08H is entered, and the serial transfer continues.
If a forced bus access occurs or a repeated START condition is
transmitted while SDA is obstructed (pulled LOW), the SIO1
hardware performs the same action as described above. In each
case, state 08H is entered after a successful START condition is
transmitted and normal serial transfer continues. Note that the CPU
is not involved in solving these bus hang-up problems.
B
US
E
RROR
A bus error occurs when a START or STOP condition is present at
an illegal position in the format frame. Examples of illegal positions
are during the serial transfer of an address byte, a data or an
acknowledge bit.
The SIO1 hardware only reacts to a bus error when it is involved in
a serial transfer either as a master or an addressed slave. When a
bus error is detected, SIO1 immediately switches to the not
addressed slave mode, releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 00H. This status
code may be used to vector to a service routine which either
attempts the aborted serial transfer again or simply recovers from
the error condition as shown in Table 13.
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