• 參數(shù)資料
    型號(hào)： P87CL52X2
    廠商： NXP Semiconductors N.V.
    英文描述： 80C51 8-bit microcontroller family
    中文描述： 80C51的8位單片機(jī)系列
    文件頁(yè)數(shù)： 27/47頁(yè)
    文件大?。?/td> 301K
    代理商： P87CL52X2
    Philips Semiconductors
    Product data
    P87CL52X2/54X2
    80C51 8-bit microcontroller family
    8K/16K OTP 256 bytes RAM ROMless low voltage
    (1.8 V to 3.3 V), low power, high speed (33 MHz)
    2003 May 14
    27
    SCON
    Address = 98H
    Reset Value = 0000 0000B
    SM0/FE
    7
    SM1
    6
    SM2
    5
    REN
    4
    TB8
    3
    RB8
    2
    Tl
    1
    Rl
    0
    Bit Addressable
    (SMOD0 = 0/1)*
    Symbol
    Function
    FE
    Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
    frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
    Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
    Serial Port Mode Bit 1
    SM0
    SM1
    Mode
    Description
    Baud Rate**
    0
    0
    0
    shift register
    f
    OSC
    /12
    0
    1
    1
    8-bit UART
    variable
    1
    0
    2
    9-bit UART
    f
    OSC
    /64 or f
    OSC
    /32
    1
    1
    3
    9-bit UART
    variable
    Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
    received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
    In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
    Given or Broadcast Address. In Mode 0, SM2 should be 0.
    Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
    The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
    In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
    In Mode 0, RB8 is not used.
    Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
    other modes, in any serial transmission. Must be cleared by software.
    Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
    the other modes, in any serial reception (except see SM2). Must be cleared by software.
    SM0
    SM1
    SM2
    REN
    TB8
    RB8
    Tl
    Rl
    NOTE:
    *SMOD0 is located at PCON6.
    **f
    OSC
    = oscillator frequency
    SU00043
    Bit:
    Figure 13. SCON: Serial Port Control Register
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