參數(shù)資料
型號(hào)： P87CL884T
廠(chǎng)商： NXP Semiconductors N.V.
英文描述： TELX microcontrollers for CT0 handset/basestation applications
中文描述： TELX微控制器CT0手機(jī)/基站應(yīng)用
文件頁(yè)數(shù)： 20/32頁(yè)
文件大?。?/td> 145K
代理商： P87CL884T
20
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
6.8
Emulation
The emulator for the P8xCL883/P8xCL884 uses the P87CL880 microcontroller in emulation mode. The P87CL880 is a
super-set of the P8xCL883/P8xCL884, i.e. it contains all the functions of the P8xCL883/P8xCL884 plus a number of
other additional functions. It should be noted that some functional differences between P87CL880 and
P8xCL883/P8xCL884 exist; see Table 12.
Table 12
Differences between functions existing in P87CL880 and P8xCL883/P8xCL884
FUNCTION
P87CL880
P8XCL883/P8XCL884
Timer 2
OTP Program Memory
RAM
EW pin (Watchdog enable)
Security concept
In-System Programming
Reset value of SFRs
POR
Frequency
Package
see P87CL880 specification
32 kbytes AFPROM
512 bytes
yes
see P87CL880 specification
no
see P87CL880 specification
hardware programmable
DC to 12.5 MHz
QFP64
see P8xCL883/P8xCL884 specification
8 kbytes EPROM or pre-programmed ROM
256 bytes
no
see P8xCL883/P8xCL884 specification
yes
see P8xCL883/P8xCL884 specification
fixed
3.58 MHz
SO28
6.9
Non-conformance
6.9.1
P
ROGRAMMING INTERFACE
/T
RANSPARENT MODE
The Transparent mode is a special operating mode of the
microcontroller used for parallel and In-System OTP
programming.
For certain combinations of data written to Port 1 (used for
control signal during parallel programming mode) the
Transparent mode may be incorrectly active during normal
operation of the microcontroller. In this case, a transition
on any of Port 0 pins can influence the read out of the
on-chip program memory, resulting in incorrect code
execution.
To avoid this problem, the InSysMode bit in the OTP
In-System Programming Register (SFR address DCH)
must
be set in the start-up sequence of the program code.
Apart from preventing incorrect operation as described
above, the setting of this bit does not affect the normal
operation.
6.9.2
L
OW
V
OLTAGE
D
ETECTION
The LVDI bit (LVDCON.6) may incorrectly be set due to a
glitch on the LVD output, when the LVD is enabled, by
changing the bits LVDCON(3:0) from ‘0000’ to any value
within the range ‘0001’ to ‘0101’. If bit EA in register IEN0
is enabled, an unwanted interrupt may occur.
A software workaround for this problem exists. During the
initialisation sequence:
Enable LVD by writing to register LVDCON
Enable LVD interrupt by writing to register IEN2
Clear the LVDI bit by writing to LVDCON a second time
Set bit EA in register IEN0 (ensures LVDI to be cleared
after initialisation).
6.9.3
E
DGE DETECTION ON
UART
In receive mode 1, 2 and 3 it is possible that an internal
setup/hold condition of a flip-flop is violated. This results in
a not detected start bit (start condition) during receive
mode. The probability of occurrence (verified on sampling
basis) is below 3%.
There is no workaround for this problem other than to use
the UART only in Mode 0 for reception.
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