參數(shù)資料
型號： P87LPC764BDH,512
廠商： NXP Semiconductors
文件頁數(shù)： 47/60頁
文件大小： 0K
描述： IC 80C51 MCU 4K OTP 20-TSSOP
產(chǎn)品培訓模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝： 75
系列： LPC700
核心處理器： 8051
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，UART/USART
外圍設備： 欠壓檢測/復位，LED，POR，WDT
輸入/輸出數(shù)： 18
程序存儲器容量： 4KB（4K x 8）
程序存儲器類型： OTP
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 6 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
包裝： 管件
產(chǎn)品目錄頁面： 706 (CN2011-ZH PDF)
其它名稱： 568-1259-5
935267867512
P87LPC764BDH
Philips Semiconductors
Product data
P87LPC764
Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
2003 Sep 03
50
DC ELECTRICAL CHARACTERISTICS (FOR P87LPC764HDH)
VDD = 4.5 V to 5.5 V; Tamb = –40°C to +125°C.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP1
MAX
UNIT
IDD
Power supply current, operating
5.0 V, 20 MHz11
15
25
mA
IID
Power supply current, Idle mode
5.0 V, 20 MHz11
6
10
mA
IPD
Power supply current, Power Down mode
5.0 V11
1
10
A
VRAM
RAM keep-alive voltage
1.5
V
VIL
Input low voltage (TTL input)
4.0 V < VDD < 6.0 V
–0.5
0.2 VDD–0.1
V
VIL1
Negative going threshold (Schmitt input)
–0.5
0.3 VDD
V
VIH
Input high voltage (TTL input)
0.2 VDD+0.9
VDD+0.5
V
VIH1
Positive going threshold (Schmitt input)
0.7 VDD
VDD+0.5
V
HYS
Hysteresis voltage
0.2 VDD
V
VOL
Output low voltage all ports5, 9
IOL = 3.2 mA, VDD = 2.7 V
0.4
V
VOL1
Output low voltage all ports5, 9
IOL = 20 mA, VDD = 2.7 V
1.0
V
VOH
Output high voltage, all ports3
IOH = –30 A, VDD = 4.5 V
VDD–0.7
V
VOH1
Output high voltage, all ports4
IOH = –1.0 mA, VDD = 2.7 V
VDD–0.7
V
CIO
Input/Output pin capacitance10
15
pF
IIL
Logical 0 input current, all ports8
VIN = 0.4 V
–50
A
ILI
Input leakage current, all ports7
VIN = VIL or VIH
±2
A
ITL
Logical 1 to 0 transition current, all ports3, 6
VIN = 2.0 V at VDD = 5.5 V
–150
–650
A
RRST
Internal reset pull-up resistor14
40
225
k
VBOLOW
Brownout trip voltage with BOV = 112
2.35
2.69
V
VBOHI
Brownout trip voltage with BOV = 0
3.45
3.99
V
VREF
Reference voltage
1.11
1.26
1.41
V
tC (VREF)
Temperature coefficient
tbd
ppm/
°C
SS
Supply sensitivity
tbd
%/V
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. See other Figures for details.
Active mode: ICC(MAX) = tbd
Idle mode: ICC(MAX) = tbd
3. Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). Does not apply to open drain pins.
4. Ports in PUSH-PULL mode. Does not apply to open drain pins.
5. In all output modes except high impedance mode.
6. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when
VIN is approximately 2 V.
7. Measured with port in high impedance mode. Parameter is guaranteed but not tested at cold temperature.
8. Measured with port in quasi-bidirectional mode.
9. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
20 mA
Maximum total IOL for all outputs:
80 mA
Maximum total IOH for all outputs:
5 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
10. Pin capacitance is characterized but not tested.
11. The IDD, IID, and IPD specifications are measured using an external clock with the following functions disabled: comparators, brownout
detect, and watchdog timer. For VDD = 3 V, LPEP = 1. Refer to the appropriate figures on the following pages for additional current drawn by
each of these functions and detailed graphs for other frequency and voltage combinations.
12. Devices initially operating at VDD = 2.7V or above and at fOSC = 10 MHz or less are guaranteed to continue to execute instructions correctly
at the brownout trip point. Initial power-on operation below VDD = 2.7 V is not guaranteed.
13. Devices initially operating at VDD = 4.0 V or above and at fOSC = 20 MHz or less are guaranteed to continue to execute instructions correctly
at the brownout trip point. Initial power-on operation below VDD = 4.0 V and FOSC > 10 MHz is not guaranteed.
14. This internal resistor is disconnected if P1.5 is used as a general purpose input pin instead of the reset pin.
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