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參數(shù)資料
| 型號： | P89C538NBBB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS single-chip 8-bit microcontrollers with FLASH program memory |
| 中文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 X 1.75 MM, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 13/35頁 |
| 文件大?。?/td> | 221K |
| 代理商： | P89C538NBBB |
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Philips Semiconductors
Preliminary specification
89C535/89C536/89C538
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
1997 Jun 05
13
Interrupt Priority Structure
The 89C535/536/538 has a 6-source two-level interrupt structure
(see Table 7). There are 2 SFRs associated with the interrupts on
the 89C535/536/538. They are the IE and IP. (See Figures 6 and 7.)
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IP.x
0
Level 0 (lowest priority)
1
Level 1 (highest priority)
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Table 7.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR
VECTOR ADDRESS
X0
1
IE0
N (L)
1
Y (T)
2
03H
T0
2
TP0
Y
0BH
X1
3
IE1
N (L)
Y (T)
13H
T1
4
TF1
Y
1BH
SP
5
R1, TI
N
23H
T2
6
TF2, EXF2
N
2BH
NOTES:
1. L = Level activated
2. T = Transition activated
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