參數(shù)資料
型號(hào)： P89LPC907FD,112
廠商： NXP Semiconductors
文件頁數(shù)： 50/51頁
文件大小： 0K
描述： IC 80C51 MCU FLASH 1K 8-SOIC
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 1
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 7.3728MHz
連通性： UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，LED，POR，WDT
輸入/輸出數(shù)： 6
程序存儲(chǔ)器容量： 1KB（1K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
包裝： 剪切帶 (CT)
配用： 622-1006-ND - SOCKET ADAPTER BOARD
其它名稱： 568-1998-1
Philips Semiconductors
P89LPC906/907/908
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 17 December 2004
8 of 51
9397 750 14467
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5.2 Pin description
Table 3:
P89LPC906 pin description
Symbol
Pin
Type
Description
P0.4 to P0.6
I/O
Port 0: Port 0 is an I/O port with a user-congurable output types. During reset Port 0
latches are congured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port conguration
selected. Each port pin is congured independently. Refer to Section 8.11.1 “Port
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
8
I/O
P0.4 — Port 0 bit 4.
I
CIN1A — Comparator positive input.
I
KBI4 — Keyboard input 4.
7
I/O
P0.5 — Port 0 bit 5.
I
CMPREF — Comparator reference (negative) input.
I
KBI5 — Keyboard input 5.
3
I/O
P0.6 — Port 0 bit 6.
O
CMP1 — Comparator 1 output.
I
KBI6 — Keyboard input 6.
P1.5
I
P1.5 — Port 1 bit 5 (input only).
1I
RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force In-System
Programming mode. When using an oscillator frequency above 12 MHz, the
reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specied level.
When system power is removed VDD will fall below the minimum specied
operating voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specied operating voltage.
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