參數(shù)資料
型號: P89LPC915HDH,129
廠商: NXP Semiconductors
文件頁數(shù): 11/11頁
文件大?。?/td> 0K
描述: IC 80C51 MCU 2KB FLASH 14TSSOP
標準包裝: 96
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,UART/USART
外圍設(shè)備: 欠壓檢測/復位,LED,POR,PWM,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 2KB(2K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b; D/A 1x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 管件
LC717A00AR
No.A2048-9/11
Pin Functions
Pin Name
I/O
Pin Functions
Pin Type
Cin0
I/O
Capacitance sensor input
Cin1
I/O
Capacitance sensor input
Cin2
I/O
Capacitance sensor input
Cin3
I/O
Capacitance sensor input
Cin4
I/O
Capacitance sensor input
Cin5
I/O
Capacitance sensor input
Cin6
I/O
Capacitance sensor input
Cin7
I/O
Capacitance sensor input
Cref
I/O
Reference capacitance input
R
AMP
VDD
VSS
Buffer
Pout0
O
Cin0 judgment result output
Pout1
O
Cin1 judgment result output
Pout2
O
Cin2 judgment result output
Pout3
O
Cin3 judgment result output
Pout4
O
Cin4 judgment result output
Pout5
O
Cin5 judgment result output
Pout6
O
Cin6 judgment result output
Pout7
O
Cin7 judgment result output
ERROR
O
Error occurrence status output
Cdrv
O
Output for capacitance sensors drive
INTOUT
O
Interrupt output
VDD
VSS
Buffer
SCL/SCK
I
Clock input (I
2C)
/ Clock input (SPI)
GAIN
I
Selection pin of the initial value of gain of the
2nd-amplifier
nCS
I
Interface selection
/ Chip select inverting input (SPI)
nRST
I
External reset signal inverting input
VDD
VSS
R
SDA/SI
I/O
Data input and output (I
2C)
/ Data input (SPI)
VDD
VSS
R
SA/SO
I/O
Slave address selection (I
2C)
/ Data output (SPI)
VDD
VSS
R
Buffer
VDD
Power supply (2.6V to 5.5V) *1
VSS
Ground (Earth) *1 *2
*
1) Inserting a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS is recommended.
In this case, the small-valued capacitor should be at least 0.1
μF, and is mounted near the LSI.
*
2) When VSS terminal is not grounded in battery-powered mobile equipment, detection sensitivity may be degraded.
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