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參數(shù)資料
| 型號(hào)： | P89LPC917FDH,129 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 2K 16-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | I²C，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 14 |
| 程序存儲(chǔ)器容量： | 2KB（2K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b; D/A 1x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | DB-TSSOP-LPC917-ND - BOARD FOR LPC917 TSSOP 622-1014-ND - BOARD FOR LPC9XX TSSOP 622-1008-ND - BOARD FOR LPC9103 10-HVSON 622-1006-ND - SOCKET ADAPTER BOARD 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART 568-3510-ND - DEMO BOARD SPI/I2C TO UART 622-1002-ND - USB IN-CIRCUIT PROG LPC9XX 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X |
| 其它名稱： | 568-2247 935276207129 P89LPC917FDH-S |
LC717A00AR
No.A2048-10/11
Details of Pin Functions
●Cin0 to Cin7
These are the capacitance-sensor-input pins. These pins are used by connecting them to the touch switch pattern. Cin
and the Cdrv wire patterns should be close to each other. By doing so, Cdrv and Cin patterns are capacitively coupled.
Therefore, LSI can detect capacitance change near each pattern as 8bit digital data.
However, if the shape of each pattern or the capacitively coupled value of Cdrv is not appropriate, it may not be able
to detect the capacitance change correctly.
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. Cin0 to Cin7 are connected to the inverting input of the 1st amplifier in the LSI.
During measurement process, channels other than the one being measured are all in “Low” condition.
Leave the unused terminals open.
●Cref
It is the reference-capacitance-input pin. It is used by connecting to the wire pattern like Cin pins or is used by
connecting any capacitance between this pin and Cdrv pin.
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. Cref is connected to the non-inverting input of the 1st amplifier in the LSI.
Due to the parasitic capacitance generated in the wire connections of Cin pins and their patterns, as well as the one
generated between the wire patterns of Cin and Cdrv pins, Cref may not detect capacitance change of each Cin pin
accurately. In this case, connect an appropriate capacitance between Cref and Cdrv to detect capacitance change
accurately.
However, if the difference between the parasitic capacitance of each Cin pin is extremely large, it may not detect
capacitance change in each Cin pin correctly.
●Pout0 to Pout7
These are the detection-result-output pins. The capacitance detection results of Cin0 to Cin7 are compared with the
threshold of the LSI. The pin outputs a “High” or a “Low” depending on the result.
●ERROR
It is the error-occurrence-status-output pin.
It outputs “Low” during normal operation. If there is a calibration error or a system error, it outputs “High” to indicate
that an error occurred.
●Cdrv
It is the output pin for capacitance sensors drive. It outputs the pulse voltage which is needed to detect capacitance at
Cin0 to Cin7.
Cdrv and Cin wire patterns should be close to each other so that they are capacitively coupled.
●INTOUT
It is the interrupt-output pin. It outputs “High” when a measurement process is completed.
Connect to a main microcomputer if necessary, and use as interrupt signal.
Leave the terminal open if not in used.
●SCL/SCK
Clock input (I2C) / Clock input (SPI)
It is the clock input pin of the I2C compatible bus or the SPI depending on the mode of operation.
If interface is not to be used, fix the pin to “High”. However, even if interface is not to be used, providing a
communication terminal on board is still recommended.
●GAIN
In this LSI, there is a two-stage amplifier that detects the changes in the capacitance and outputs analog-amplitude
values. It is the selection pin of the initial value of gain of the 2nd amplifier.
Even if this LSI is used alone, gain setting can still be selected through this terminal. At initialization of the LSI, it is
set to 7-times higher than the minimum setting when GAIN pin is “Low”, and is set to 14-times higher than the
minimum setting when GAIN pin is “High”.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89LPC917FDH-S | 制造商:NXP Semiconductors 功能描述:MCU 8-bit P89 80C51 CISC 2KB Flash 2.5V/3.3V 16-Pin TSSOP |
| P89LPC920 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM |
| P89LPC9201 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB 3 V byte-erasable flash with 8-bit ADC |
| P89LPC9201FDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB 3 V byte-erasable flash with 8-bit ADC |
| P89LPC9201FDH,112 | 功能描述:8位微控制器 -MCU MCU 8-Bit CISC 2KB Flash2.5V/3.3V 20Pin RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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