參數(shù)資料
型號(hào): P89LPC921FN,112
廠商: NXP Semiconductors
文件頁數(shù): 22/46頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 4K 20-DIP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 18
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-2248-5
935280399112
P89LPC921FN
Philips Semiconductors
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 08 — 15 December 2004
29 of 46
9397 750 14469
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.20 Analog comparators
Two analog comparators are provided on the P89LPC920/921/922/9221. Input and
output options allow use of the comparators in a number of different congurations.
Comparator operation is such that the output is a logical one (which may be read in a
register and/or routed to a pin) when the positive input (one of two selectable pins) is
greater than the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a zero. Each comparator may be congured to
cause an interrupt when the output value changes.
The overall connections to both comparators are shown in Figure 10. The
comparators function to VDD = 2.4 V.
When each comparator is rst enabled, the comparator output and interrupt ag are
not guaranteed to be stable for 10 microseconds. The corresponding comparator
interrupt should not be enabled during that time, and the comparator interrupt ag
must be cleared before the interrupt is enabled in order to prevent an immediate
interrupt service.
When a comparator is disabled the comparator’s output, COx, goes HIGH. If the
comparator output was LOW and then is disabled, the resulting transition of the
comparator output from a LOW to HIGH state will set the comparator ag, CMFx.
This will cause an interrupt if the comparator interrupt is enabled. The user should
therefore disable the comparator interrupt prior to disabling the comparator.
Additionally, the user should clear the comparator ag, CMFx, after disabling the
comparator.
8.20.1
Internal reference voltage
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to
as VREF, is 1.23 V ±10%.
Fig 10. Comparator input and output connections.
Comparator 1
CP1
CN1
(P0.4) CIN1A
(P0.3) CIN1B
(P0.5) CMPREF
VREF
OE1
Change Detect
CO1
CMF1
Interrupt
002aaa422
CMP1 (P0.6)
EC
Change Detect
CMF2
Comparator 2
OE2
CO2
CMP2 (P0.0)
CP2
CN2
(P0.2) CIN2A
(P0.1) CIN2B
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