參數(shù)資料
型號: P89LPC9341FDH,512
廠商: NXP Semiconductors
文件頁數(shù): 54/94頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 28-TSSOP
標準包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b; D/A 2x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
配用: 568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 935288632512
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
58 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.30.10 Hardware activation of the bootloader
The bootloader can also be executed by forcing the device into ISP mode during a
power-on sequence (see the P89LPC9331/9341/9351/9361 User manual for specific
information). This has the same effect as having a non-zero status byte. This allows an
application to be built that will normally execute user code but can be manually forced into
ISP operation. If the factory default setting for the boot is changed, it will no longer point to
the factory pre-programmed ISP bootloader code. After programming the flash, the status
byte should be programmed to zero in order to allow execution of the user’s application
code beginning at address 0000H.
7.31 User configuration bytes
Some user-configurable features of the P89LPC9331/9341/9351/9361 must be defined at
power-up and therefore cannot be set by the program after start of execution. These
features are configured through the use of the flash byte UCFG1 and UCFG2. Please see
the P89LPC9331/9341/9351/9361 User manual for additional details.
7.32 User sector security bytes
There are 4/8/6 User Sector Security Bytes on the P89LPC9331/9341/9351/9361. Each
byte corresponds to one sector. Please see the P89LPC9331/9341/9351/9361 User
manual for additional details.
8.
ADC
8.1 General description
The P89LPC9331/9341/9351/9361 has two 8-bit, 4-channel multiplexed successive
approximation analog-to-digital converter modules. An on-chip temperature sensor is
integrated within ADC0 and operates over wide temperature. In P89LPC9351/9361, two
high-speed programmable gain amplifiers (PGA) are integrated. The PGAs provide
selectable gains of 2x, 4x, 8x, or 16x. A block diagram of the ADC is shown in Figure 23
Each ADC consists of a 4-input multiplexer which feeds a sample-and-hold circuit
providing an input signal to comparator inputs. The control logic in combination with the
SAR drives a digital-to-analog converter which provides the other input to the comparator.
The output of the comparator is fed to the SAR.
8.2 Features and benefits
Two 8-bit, 4-channel multiplexed input, successive approximation ADCs.
P89LPC9341
1FH
1F00H
1E00H to 1FFFH
1C00H to 1FFFH
P89LPC9351
1FH
1F00H
1E00H to 1FFFH
1C00H to 1FFFH
P89LPC9361
3FH
3F00H
3E00H to 3FFFH
3C00H to 3FFFH
Table 10.
Default boot vector values and ISP entry points …continued
Device
Default
boot vector
Default
bootloader
entry point
Default bootloader
code range
1 kB sector
range
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