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參數(shù)資料
| 型號： | P89LPC9351FA,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 53/94頁 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 28-PLCC |
| 產(chǎn)品培訓模塊： | LPC9351/9321 Overview |
| 標準包裝： | 2,368 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 8x8b; D/A 2x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-PLCC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1014-ND - BOARD FOR LPC9XX TSSOP 622-1006-ND - SOCKET ADAPTER BOARD 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART 568-3510-ND - DEMO BOARD SPI/I2C TO UART 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X 568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY |
| 其它名稱： | 568-4701-5 935287627112 P89LPC9351FA |
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P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
57 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
without additional components. Two methods are available to accomplish IAP. A set of
predefined IAP functions are provided in a Boot ROM and can be called through a
common interface, PGM_MTP. Several IAP calls are available for use by an application
program to permit selective erasing and programming of flash sectors, pages, security
bits, configuration bytes, and device ID. These functions are selected by setting up the
microcontroller’s registers before making a call to PGM_MTP at FF03H. The Boot ROM
occupies the program memory space at the top of the address space from FF00H to
FEFFH, thereby not conflicting with the user program memory space.
In addition, IAP operations can be accomplished through the use of four SFRs consisting
of a control/status register, a data register, and two address registers. Additional details
may be found in the P89LPC9331/9341/9351/9361 User manual.
7.30.8 ISP
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LPC9331/9341/9351/9361 through the serial
port. This firmware is provided by NXP and embedded within each
P89LPC9331/9341/9351/9361 device. The NXP ISP facility has made in-system
programming in an embedded application possible with a minimum of additional expense
in components and circuit board area. The ISP function uses five pins (VDD, VSS, TXD,
RXD, and RST). Only a small connector needs to be available to interface your application
to an external circuit in order to use this feature.
7.30.9 Power-on reset code execution
The P89LPC9331/9341/9351/9361 contains two special flash elements: the Boot Vector
and the Boot Status bit. Following reset, the P89LPC9331/9341/9351/9361 examines the
contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution
starts at location 0000H, which is the normal start address of the user’s application code.
When the Boot Status bit is set to a value other than zero, the contents of the Boot Vector
are used as the high byte of the execution address and the low byte is set to 00H.
Table 10 shows the factory default Boot Vector setting for these devices. A
factory-provided bootloader is pre-programmed into the address space indicated and
uses the indicated bootloader entry point to perform ISP functions. This code can be
erased by the user.
Remark: Users who wish to use this loader should take precautions to avoid erasing the
1 kB sector that contains this bootloader. Instead, the page erase function can be used to
erase the first eight 64-byte pages located in this sector.
A custom bootloader can be written with the Boot Vector set to the custom bootloader, if
desired.
Table 10.
Default boot vector values and ISP entry points
Device
Default
boot vector
Default
bootloader
entry point
Default bootloader
code range
1 kB sector
range
P89LPC9331
0FH
0F00H
0E00H to 0FFFH
0C00H to 0FFFH
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相關代理商/技術參數(shù) |
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| P89LPC9351FDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 8-bit ADC |
| P89LPC9351FDH,518 | 功能描述:8位微控制器 -MCU Enhanced LPC935 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89LPC935FA | 制造商:NXP Semiconductors 功能描述:IC MCU 8BIT 80C51 8K FLASH PLCC28 |
| P89LPC935FA,129 | 功能描述:8位微控制器 -MCU 80C51 8K FL 768B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89LPC935FA129 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ LCC-28 |
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