參數(shù)資料
型號: P89LPC9361FDH,518
廠商: NXP Semiconductors
文件頁數(shù): 11/94頁
文件大?。?/td> 0K
描述: IC MCU 80C51 16KB FLASH 28TSSOP
標準包裝: 1
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b; D/A 2x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 標準包裝
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P8
9LPC
9331_
9341
_935
1_93
61
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er
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NXP
B.V
.
2012.
Al
lr
ig
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ts
res
er
v
ed.
Produ
ct
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at
a
sheet
Rev
.5.1
20
Au
gu
st
2012
19
o
f94
N
X
P
Semi
conductor
s
P89LPC9331/9341/9351/9361
8-
bit
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with
a
cce
lerat
e
d
tw
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80C5
1
core
[1]
All ports are in input only (high-impedance) state after power-up.
[2]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[3]
The RSTSRC register reflects the cause of the P89LPC9331/9341 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the
power-on reset value is x011 0000.
[4]
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
[5]
On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]
The only reset sources that affect these SFRs are power-on reset and watchdog reset.
WDL
Watchdog load
C1H
FF
1111 1111
WFEED1
Watchdog
feed 1
C2H
WFEED2
Watchdog
feed 2
C3H
Table 4.
Special function registers - P89LPC9331/9341 …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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