• 參數(shù)資料
    型號(hào): P89LPC938FA
    廠(chǎng)商: NXP SEMICONDUCTORS
    元件分類(lèi): 微控制器/微處理器
    英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable Flash with 10-bit A/D converter
    中文描述: 8-BIT, FLASH, 18 MHz, MICROCONTROLLER, PQCC28
    封裝: PLASTIC, MS-018, SOT-261-2, LCC-28
    文件頁(yè)數(shù): 21/68頁(yè)
    文件大?。?/td> 318K
    代理商: P89LPC938FA
    9397 750 14051
    Koninklijke Philips Electronics N.V. 2005. All rights reserved.
    Product data sheet
    Rev. 01 — 25 February 2005
    21 of 68
    Philips Semiconductors
    P89LPC938
    8-bit microcontroller with 10-bit A/D converter
    7.7 CCLK wake-up delay
    The P89LPC938 has an internal wake-up timer that delays the clock until it stabilizes
    depending on the clock source used. If the clock source is any of the three crystal
    selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus
    60 to 100
    μ
    s. If the clock source is either the internal RC oscillator, watchdog oscillator, or
    external clock, the delay is 224 OSCCLK cycles plus 60
    μ
    s to 100
    μ
    s.
    7.8 CCLK modification: DIVM register
    The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
    register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
    CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
    retain the ability to respond to events that would not exit Idle mode by executing its normal
    program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
    where Power-down mode would otherwise be used. The value of DIVM may be changed
    by the program at any time without interrupting code execution.
    7.9 Low power select
    The P89LPC938 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is
    8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power
    consumption further. On any reset, CLKLP is ‘0’ allowing highest performance access.
    This bit can then be set in software if CCLK is running at 8 MHz or slower.
    7.10 Memory organization
    The various P89LPC938 memory spaces are as follows:
    DATA
    128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect
    addressing, using instructions other than MOVX and MOVC. All or part of the Stack
    may be in this area.
    IDATA
    Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via
    indirect addressing using instructions other than MOVX and MOVC. All or part of the
    Stack may be in this area. This area includes the DATA area and the 128 bytes
    immediately above it.
    SFR
    Special Function Registers. Selected CPU registers and peripheral control and status
    registers, accessible only via direct addressing.
    XDATA
    ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space
    addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this
    space could be implemented on-chip. The P89LPC938 has 512 bytes of on-chip
    XDATA memory, plus extended SFRs located in XDATA.
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