參數資料
型號: P89LPC954FBD44,151
廠商: NXP Semiconductors
文件頁數: 24/69頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44LQFP
標準包裝: 160
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數: 40
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數據轉換器: A/D 8x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
配用: 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-7917
568-7917-ND
568-8269
935284303151
P89LPC954FBD44,151-ND
P89LPC954FBD44-S
P89LPC954FBD44-S-ND
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
30 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
An open-drain port pin has a Schmitt triggered input that also has a glitch suppression
circuit.
7.13.1.3
Input-only conguration
The input-only port conguration has no output drivers. It is a Schmitt triggered input that
also has a glitch suppression circuit.
7.13.1.4
Push-pull output conguration
The push-pull output conguration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a port output. A push-pull port pin has a
Schmitt triggered input that also has a glitch suppression circuit.
7.13.2 Port 0 analog functions
The P89LPC952/954 incorporates two Analog Comparators. In order to give the best
analog function performance and to minimize power consumption, pins that are being
used for analog functions must have the digital outputs and digital inputs disabled.
Digital outputs are disabled by putting the port output into the Input-Only
(high-impedance) mode.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.
On any reset, PT0AD[1:5] defaults to ‘0’s to enable digital functions.
7.13.3 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different from
the LPC76x series of devices.
After power-up, all I/O pins except P1.5, may be congured by software.
Pin P1.5 is input only. Pins P1.2 and P1.3 are congurable for either input-only or
open-drain.
Every output on the P89LPC952/954 has been designed to sink typical LED drive current.
However, there is a maximum total output current for all ports which must not be
exceeded. Please refer to Table 11 for detailed specications.
All ports pins that can function as an output have slew rate controlled outputs to limit noise
generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
7.14 Power monitoring functions
The P89LPC952/954 incorporates power monitoring functions designed to prevent
incorrect operation during initial power-up and power loss or reduction during operation.
This is accomplished with two hardware functions: Power-on detect and brownout detect.
7.14.1 Brownout detection
The brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a brownout detection to cause a processor reset,
however it may alternatively be congured to generate an interrupt.
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