參數(shù)資料
型號: P89V51RC2FA,512
廠商: NXP Semiconductors
文件頁數(shù): 26/80頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 32K 44-PLCC
產(chǎn)品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 26
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-2428-5
935277727512
P89V51RC2FA
P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
32 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
6.5.1 Capture mode
In the Capture mode there are two options which are selected by bit EXEN2 in T2CON. If
EXEN2 = 0 Timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which
upon overowing sets bit TF2, the Timer 2 overow bit.
The capture mode is illustrated in Figure 12.
4
TCLK
Transmit clock ag. When set, causes the UART to use Timer 2
overow pulses for its transmit clock in modes 1 and 3. TCLK = 0
causes Timer 1 overows to be used for the transmit clock.
3
EXEN2
Timer 2 external enable ag. When set, allows a capture or reload to
occur as a result of a negative transition on T2EX if Timer 2 is not
being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
2
TR2
Start/stop control for Timer 2. A logic ‘1’ enables the timer to run.
1C/T2
Timer or counter select. (Timer 2)
0 = internal timer (fosc / 6)
1 = external event counter (falling edge triggered; external clock’s
maximum rate = fosc / 12
0
CP/RL2
Capture/Reload ag. When set, captures will occur on negative
transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will
occur either with Timer 2 overows or negative transitions at T2EX
when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is
ignored and the timer is forced to auto-reload on Timer 2 overow.
Table 22.
T2MOD - Timer 2 mode control register (address C9H) bit allocation
Not bit addressable; Reset value: XX00 0000B
Bit
7
6
5
4
3
2
1
0
Symbol
-
T2OE
DCEN
Table 23.
T2MOD - Timer 2 mode control register (address C9H) bit description
Bit
Symbol
Description
7 to 2
-
Reserved for future use. Should be set to ‘0’ by user programs.
1
T2OE
Timer 2 Output Enable bit. Used in programmable clock-out mode
only.
0
DCEN
Down Count Enable bit. When set, this allows Timer 2 to be congured
as an up/down counter.
Table 21.
T2CON - Timer/counter 2 control register (address C8H) bit description …continued
Bit
Symbol
Description
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