參數(shù)資料
型號: P89V662FA,512
廠商: NXP Semiconductors
文件頁數(shù): 9/90頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 32K 44-PLCC
產(chǎn)品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 26
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
其它名稱: 568-2434-5
935280831512
P89V662FA
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
17 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.2.3 Reset
At initial power-up, the port pins will be in a random state until the oscillator has started
and the internal reset algorithm has weakly pulled all pins high. Powering up the device
without a valid reset could cause the MCU to start executing instructions from an
indeterminate location. Such undefined states may inadvertently corrupt the code in the
flash. A system reset will not affect the on-chip RAM while the device is running, however,
the contents of the on-chip RAM during power-up are indeterminate.
When power is applied to the device, the RST pin must be held high long enough for the
oscillator to start-up (usually several milliseconds for a low frequency crystal), in addition
to two machine cycles for a valid power-on reset. An example of a method to extend the
RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 F
capacitor and to VSS through an 8.2 k resistor as shown in Figure 6.
During initial power the POF flag in the PCON register is set to indicate an initial power-up
condition. The POF flag will remain active until cleared by software.
Following a reset condition, under normal conditions, the MCU will start executing code
from address 0000H in the user’s code memory. However if either the PSEN pin was low
when reset was exited, or the Status Bit was set = 1, the MCU will start executing code
from the boot address. The boot address is formed using the value of the boot vector as
the high byte of the address and 00H as the low byte.
Fig 5.
Dual data pointer organization
Table 8.
AUXR1 - Auxiliary register 1 (address A2H) bit allocation
Not bit addressable; Reset value 00H
Bit
7
6
5
4
3
2
1
0
Symbol
--
GF2
0
-DPS
Table 9.
AUXR1 - Auxiliary register 1 (address A2H) bit description
Bit
Symbol
Description
7 to 4
-
Reserved for future use. Should be set to ‘0’ by user programs.
3
GF2
General purpose user-defined flag.
2
0
This bit contains a hard-wired ‘0’. Allows toggling of the DPS bit by
incrementing AUXR1, without interfering with other bits in the register.
1
-
Reserved for future use. Should be set to ‘0’ by user programs.
0
DPS
Data pointer select. Chooses one of two Data Pointers for use by the
program. See text for details.
DPL
82H
DPS = 0
→ DPTR0
DPS = 1
→ DPTR1
external data memory
DPS
002aaa518
DPH
83H
DPTR0
DPTR1
AUXR1 / bit0
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