
MC9S12XE-Family Reference Manual , Rev. 1.07
Freescale Semiconductor
593
Chapter 15
Inter-Integrated Circuit (IICV3) Block Description
15.1
Introduction
Theinter-ICbus(IIC)isatwo-wire,bidirectionalserialbusthatprovidesasimple,efficientmethodofdata
exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of
connections between devices, and eliminates the need for an address decoder.
This bus is suitable for applications requiring occasional communications over a short distance between a
number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for
further expansion and system development.
The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is
capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The
maximum communication length and the number of devices that can be connected are limited by a
maximum bus capacitance of 400 pF.
15.1.1
Features
The IIC module has the following key features:
Compatible with I2C bus standard
Multi-master operation
Software programmable for one of 256 different serial clock frequencies
Software selectable acknowledge bit
Interrupt driven byte-by-byte data transfer
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Start and stop signal generation/detection
Repeated start signal generation
Version
Number
Date
Author
Description of Changes
1.0
1.3
1.4
May-20-2005
Jul-28-2006
Nov-17-2006
Initial. Distributed only within Freescale
Update flow-chart of interrupt routine for 10-bit address
Revise Table1-5