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參數(shù)資料
| 型號： | PACVGA203QR |
| 廠商： | California Micro Devices Corporation |
| 英文描述： | VGA Port Companion Circuit |
| 中文描述： | VGA端口伴侶電路 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 168K |
| 代理商： | PACVGA203QR |
2004 California Micro Devices Corp. All rights reserved.
12/07/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
7
PACVGA203
Application Information
Figure 3. Typical Connection Diagram
A resistor may be necessary between the V
CC
3 pin and ground if protection against a stream of ESD pulses is
required while the PACVGA203 is in the power-down state. The value of this resistor should be chosen such that
the extra charge deposited into the V
CC
3 bypass capacitor by each ESD pulse will be discharged before the next
ESD pulse occurs. The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one pulse per
second. When the PACVGA203 is in the power-up state, an internal discharge resistor is connected to ground via
an FET switch for this purpose.
For the same reason, V
CC
1 and V
CC
4 may also require bypass capacitor discharging resistors to ground if there
are no other components in the system to provide a discharge path to ground.
GNDA, the reference voltage for the 75
resistors is not connected internally to GNDD and should ideally be con-
nected to the ground of the video DAC IC.
Red
Grn
R1
R2
8
9
10
19
21
16
17
7
6
14
V
CC
3 V_BIAS
2
12
V
CC
2 V
CC
1
V
V
H-Sync
V-Sync
DDC_Data
DDC_Clk
Blue
H-Sync
V-Sync
DDC_Data
DDC_Clk
R
G
B
PACVGA203
GNDA
GNDD
DDC_IN1
DDC_IN2
SYNC_IN1
SYNC_IN2
TERM_1
TERM_2
TERM_3
3
4
5
VIDEO_1
VIDEO_2
VIDEO_3
V
V
V
0.2uF
V
CC
4
PWR_UP
DDC_OUT1
DDC_OUT2
SYNC_OUT1
SYNC_OUT2
18
15
22
20
VIDEO_DAC_V
CC
13
0.2uF
GNDD
0.2uF
0.2uF
GNDD
SD1
SD2
24
S
S
23
11
1
DDC_V
CC
5V
VF** - VIDEO EMI Filter
SF** - SYNC EMI Filter
SR* - external resistor to
match video cable
characteristic
impedance.
SR*
SR*
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