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參數(shù)資料
| 型號： | PALCE20V8H-5JC/5 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | EE CMOS 24-Pin Universal Programmable Array Logic |
| 中文描述： | EE PLD, 5 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 20/25頁 |
| 文件大小： | 479K |
| 代理商： | PALCE20V8H-5JC/5 |
4
PALCE20V8 Family
USE
GAL
DEVICES
FOR
NEW
DESIGNS
CONFIGURATION OPTIONS
Each macrocell can be congured as one of the following: registered output, combinatorial
output, combinatorial I/O or dedicated input. In the registered output conguration, the output
buffer is enabled by the OE pin. In the combinatorial conguration, the buffer is either controlled
by a product term or always enabled. In the dedicated input conguration, the buffer is always
disabled. A macrocell congured as a dedicated input derives the input signal from an adjacent
I/O.
The macrocell congurations are controlled by the conguration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0
determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will
emulate a PAL20R8 family or a combinatorial device. Within each macrocell, SL0x, in conjunction
with SG1, selects the conguration of the macrocell and SL1x sets the output as either active low
or active high.
The conguration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0
and MC7, SG0 replaces SG1 on the feedback multiplexer.
These congurations are summarized in Table 1 and illustrated in Figure 2.
If the PALCE20V8 is congured as a combinatorial device, the CLK and OE pins may be available
as inputs to the array. If the device is congured with registers, the CLK and OE pins cannot be
used as data inputs.
Registered Output Conguration
The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered
conguration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1x. SL1x is an input to the exclusive-OR gate which is the D input to the ip-
op. SL1x is programmed as 1 for inverted output or 0 for non-inverted output. The ip-op is
loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The
output buffer is enabled by OE.
Combinatorial Congurations
The PALCE20V8 has three combinatorial output congurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control settings are SG0 = 1, SG1 = 0, and SL0x = 0. All eight product terms are available to
the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode.
Note:
1. The pin number without parentheses refers to the SKINNY DIP package. The pin number in parentheses refers to the PLCC
package.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PALCE20V8H-5JI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8H-5JI4 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8H-5JI5 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8H-5PC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8H-5PC4 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
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