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參數(shù)資料
| 型號(hào)： | PALCE20V8Q-20JI/4 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | EE CMOS 24-Pin Universal Programmable Array Logic |
| 中文描述： | EE PLD, 20 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 479K |
| 代理商： | PALCE20V8Q-20JI/4 |
22
PALCE20V8 Family
USE
GAL
DEVICES
FOR
NEW
DESIGNS
POWER-UP RESET
The PALCE20V8 has been designed with the capability to reset during system power-up.
Following power-up, all ip-ops will be reset to LOW. The output state will be HIGH
independent of the logic polarity. This feature provides extra exibility to the designer and is
especially valuable in simplifying state machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide
range of ways VCC can rise to its steady state, two conditions are required to ensure a valid
power-up reset. These conditions are:
x
The VCC rise must be monotonic.
x
Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter Symbol
Parameter Descriptions
Min
Max
Unit
tPR
Power-Up Reset Time
1000
ns
tS
Input or Feedback Setup Time
See Switching Characteristics
tWL
Clock Width LOW
tPR
tWL
tS
4 V
VCC
Power
Registered
Output
Clock
16491E-15
Figure 2. Power-Up Reset Waveform
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PALCE20V8Q-20JI5 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8Q-20PC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8Q-20PC4 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8Q-20PC5 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
| PALCE20V8Q-20PI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:EE CMOS 24-Pin Universal Programmable Array Logic |
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