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| 型號(hào)： | PC-77DS1-8CS210-01 |
| 英文描述： | Converter |
| 中文描述： | 轉(zhuǎn)換器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 172K |
| 代理商： | PC-77DS1-8CS210-01 |
Apex Signal,
A Division of NAI, Inc.
631.567.1100/631.567.1823(fax) 3-20-01 S 7 7DS1 A001 REV A 1.2
170 Wilbur Place, Bohemia, NY, 11716,USA
www.naii.com
/ e-mail:sales@naii.com Code:OVGU1 Page 5 of 8
Status, Test:
Check the corresponding bit of the Test Status Register at page 1, 16h, for status of BIT Testing for
each active channel. A ”1” means Accuracy OK; “0” failed (test cycle takes 2 seconds for accuracy error).
Status, Ref:
Check the corresponding bit of the Ref Status Register at page 1, 14h, for status of the reference input
for each active channel. A ”1” =Ref. ON, “0” = Ref. Loss (Reference loss is detected after 2 seconds).
Status, Sig:
Check the corresponding bit of the Sig Status Register at page 1, 15h, for status of the input signals for
each active channel. A "1" = Signal ON, “0” = Signal loss (Signal loss is detected after 2 seconds).
Soft Reset
(Level sensitive): Writing “1” to page 2, 1Ch/1Dh initiates and holds software reset state. Then, writing “0” initiates
reboot (takes 400 ms). This function is equivalent to a power-on self-test.
Watchdog Timer:
This feature monitors the watchdog timer register at page 2, 1A/1Bh. When it detects that a
code has been received, that code will be inverted within 100 μSec. The inverted code stays in the register until
replaced by a new code. User, after 100 μSec. should look for the inverted code to confirm that the processor is
operating.
Optional Reference Supply:
For frequency,
write a 16-bit word (Ex: 400 Hz = 1 1001 0000) to address page 1,
10/11h. For voltage, write an 16-bit word (Ex: 26.1 Vrms =1 0000 0101) with Lsb=0.1 Vrms, to address page 1,
12/13h. It is recommended that user program the required frequency before setting the output voltage.
Serial Number:
At page 2, 02/03h, is read as a 16-bit binary word.
Date Code:
Read as a decimal number at
page 2, 04/05h.
The four digits represent YYWW (Year,Year,Week.Week
Rev:
At page 1, 06/07h.
Example
0
0
0
0
1
1
0
0
DSP Rev 1.1
FPGA Rev 3
Front panel Connectors:
DC37P, Mate: DC37S
This connector is used when six (6) or fewer channels are specified
Pin Ch. 1
Pin Ch. 2
Pin Ch. 3 Pin Ch. 4
Pin Ch. 5 Pin Ch. 6 Pin
19
S1
16 S1
13 S1
10 S1
7
S1
4
S1
37
S2
34 S2
31 S2
28 S2
25 S2
22 S2
18
S3
15 S3
12 S3
9
S3
6
S3
3
S3
36
S4
33 S4
30 S4
27 S4
24 S4
21 S4
17
RHi
14
RHi
11
RHi
8
RHi
5
RHi
2
RHi
35
RLo
32
RLo
29
RLo
26
RLo
23
RLo
20
RLo
DD-50P, Mate: DD-50S
This connector is used when seven (7) or eight (8) channels are specified
Pin Ch. 1
Pin Ch. 2
Pin Ch. 3 Pin Ch. 4
Pin Ch. 5 Pin Ch. 6 Pin Ch. 7 Pin Ch. 8
16
S1
32 S1
29 S1
26 S1
23 S1
20 S1
17
S2
48 S2
45 S2
42 S2
39 S2
36 S2
15
S3
31 S3
28 S3
25 S3
22 S3
19 S3
50
S4
47 S4
44 S4
41 S4
38 S4
35 S4
33
RHi
30
RHi
27
RHi
24
RHi
21
RHi
18
RHi
49
RLo
46
RLo
43
RLo
40
RLo
37
RLo
34
RLo
S4 pins used only with Resolvers. Do not connect to any undesignated pins.
*These inputs are supplied as individual reference inputs ONLY when specified in the part number.
The Standard output connector for a 2, 4, or 6 channel card, is the 37 pin (DC-37P) connector, however the 50 pin
(DD-50P) connector can be ordered as an option, allowing separate pins for the output of the on board reference.
15 14 13 12 11 10
9
8
7
0
6
0
5
1
4
1
3
0
2
0
1
0
0
1
1
PC Rev
1 Chassis
Pin
14 RefHi
1 RefLo
2 S1
3 S2
4 S3
5 S4
6
RHi
7
RLo
8 S1
9 S2
10 S3
11 S4
12
RHi
13
RLo
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